PS20230 Datasheet, PDF (12/26 Pages) List of Unclassifed Manufacturers – COFDM demodulator with USB interface for PC-TV

PS20230
6 8051 Microprocessor
The PS20230 is controlled by an internal 8051-compatible microprocessor. This is connected to 3 internal
memories. The “Internal RAM” is 256 bytes. The “Program RAM” is 12 Kbytes. The “Data RAM” (or
“External RAM”) is 4Kbytes. There is no ROM inside the PS20230. The Program RAM can be written-to
by the 8051 and by the 2 -wire bus controller. The Data RAM can be written-to and read-from by the USB
controller. The Data RAM can be read by PID Filter.
The 8051 is clocked at 30 MHz and the basic instruction cycle is four 30 MHz cycles. There are 3 timers
in the 8051. There are no serial ports. There are 7 interrupts used in the PS20230:
Name
INT0_N
INT1_N
INT2
INT3_N
INT4
INT5_N
SUSPI
Sensitive
Edge
Level
Edge
Edge or level
Level
Edge or level
Level
Purpose
Infra-red falling edge detection
USB interrupts
Infra-red rising edge detection
Demodulator interrupts
2-wire bus and PID Filter interrupts
External interrupt input from GPP(7)
Suspend interrupt
6.1 Internal data memory
Internal Data Memory is mapped in Error! Reference source not found. The memory space is shown
divided into three blocks which are generally referred to as the Lower 128, the Upper 128, and SFR
space.
Internal Data Memory addresses are always one byte wide, which implies an address space of only 256
bytes. However, the addressing modes for internal RAM can in fact accommodate 384 bytes, using a
simple trick. Direct addresses higher than 7FH are one memory space, and indirect addresses higher
than 7FH access a different memory space. Thus Figure 6 shows the Upper 128 and SFR (Special
function register) space occupying the same block of addresses 80H through FFH, although they are
physically separate entities.
The lower 128 bytes of RAM are as mapped in Figure 6.
The lowest 32 bytes are grouped into 4 banks of 8 registers (R0 – R7) . Two bits in the Program Status
Word (PSW) select which register bank is in use. This allows more efficient use of code space, since
register instructions are shorter than instructions that use direct addressing.
The next 16 bytes above the register bank form a block of bit-addressable memory apace. The 8051
instruction set includes a selection of single-bit instructions, and the 128 bits in this area can be directly
addressed by these instructions. The bit addresses in this area are 00H through 7FH.
All of the bytes in the Lower 128 can be accessed by either direct or indirect addressing. The Upper 128
can only be accessed by indirect addressing.
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