M5123 Datasheet, PDF (92/121 Pages) List of Unclassifed Manufacturers – Mega I/O Controller with Plug & Play

--Preliminary, Confidential, Proprietary--
Acer Laboratories Inc.
M512x : Mega I/O Controller with PnP
Section 9 : Common I/O Ports
The M512x has 22 independently programmable common I/O ports (CIO). Each CIO port is represented as a bit in one of three
8-bit registers, CIO1, CIO2 or CIO3. Only 6 bits of CIO2 are implemented. Each CIO port and its alternate function is listed in
table below.
CIO Port
CIO10
CIO11
CIO12
CIO13
CIO14
CIO15
CIO16
CIO17
CIO20
CIO21
CIO22
CIO23
CIO24
CIO25
CIO30
CIO31
CIO32
CIO33
CIO34
CIO35
CIO36
CIO37
Alternate Function
Interrupt Steering
Interrupt Steering
IRRX Input
IRTX Output
GATEA20 Output
RC Reset Output
I²C Interface CLK Output
I²C Interface DATA I/O
Keylock Input
KBC clock source Input
CS0J Output
CS1J Output
ALT_KCLK I/O
ALT_KDAT I/O
ALT_MCLK I/O
ALT_MDAT I/O
ALT_KBC select Input
Register Assignment
CIO1, bit 0
CIO1, bit 1
CIO1, bit 2
CIO1, bit 3
CIO1, bit 4
CIO1, bit 5
CIO1, bit 6
CIO1, bit 7
CIO2, bit 0
CIO2, bit 1
CIO2, bit 2
CIO2, bit 3
CIO2, bit 4
CIO2, bit 5
CIO3, bit 0
CIO3, bit 1
CIO3, bit 2
CIO3, bit 3
CIO3, bit 4
CIO3, bit 5
CIO3, bit 6
CIO3, bit 7
CIO registers CIO1, CIO2 and CIO3 can be accessed by the host when the chip is in the normal run mode; i.e., not in the
configuration mode. The host uses an index and data register to access the CIO registers. The power on default index and data
registers are 0xEA and 0xEB respectively. When the chip is in configuration mode, these index and data registers are used to
access the internal configuration registers. In configuration mode, the index address may be programmed to reside on address
0xE0, 0xE2, 0xE4 or 0xEA. The data address is automatically set to the index address + 1. Upon exiting the configuration mode,
the new Index and Data registers are used to access registers CIO1, CIO2 and CIO3.
To access the CIO1 register the host should first make sure the chip is in the normal (run) mode. Then it should perform an IOW
of 0x01 to the Index register (at 0xEX) to select CIO1 and then read or write the Data register (at Index+1) to access the CIO1
register.
To access CIO2 the host should perform an IOW of 0x02 to the Index register and then access CIO2 through the Data register.
To access CIO3 the host should perform an IOW of 0x03 to the Index register and then access CIO3 through the Data register.
Register
Index
Data
Address
0xE0,0xE2,
0xE4,0xEA
0xE1,0xE3,
0xE5,0xEB
Normal (Run) Mode
0x01
0x02
access
CIO1
to access
CIO2
0x03
Config Mode
0x00-0xFF
to access to access to internal Config
CIO3
registers
CIO ports can assume alternate functions such as input-type, output-type or I/O type. The CIO port structure for each type is
illustrated in the following figures.
Page 92
07-02-1997 Document Number: 512xDS02.doc
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