M5123 Datasheet, PDF (7/121 Pages) List of Unclassifed Manufacturers – Mega I/O Controller with Plug & Play

Acer Laboratories Inc.
M512x : Mega I/O Controller with PnP
--Preliminary, Confidential, Proprietary--
2.2 Pin Description
Table 2-1 lists the functions of all M512x pins. A low represents a logic 0 (0V nominal) and a high represents a logic 1 (+2.4V
nominal).
Table 2-1
M512x Pin Description Table
Name
Number
Type
HOST Processor Interface
SD0-SD7 70-72
I/O
IORJ
68
I
IOWJ
69
I
AEN
70
I
SA0-SA15 41-53, 27-29 I
DACK0J-
DACK3J
DRQ0-
DRQ3
81,83,85,87 I
82,84,86,88 O
TC
89
I
IRQ1,
IRQ3-12,
IRQ14-15
MR
67,66,65,64, O
63,62,61,59,
58,57,56,55,
54
80
IS
Floppy Disk Interface
RDATAJ 17
IS
WGATEJ 12
O
WDATAJ 11
O
HDSELJ
13
O
DIRJ
9
O
STEPJ
10
O
DSKCHGJ 18
IS
Description
Data bus. These signals are used by the host microprocessor to transmit data
to and from the M512x. These pins are in high impedance state when not in the
output mode.
I/O Read. This active low signal is issued by the host microprocessor to
indicate a read operation.
I/O Write. This active low signal is issued by the host microprocessor to
indicate a write operation.
Address Enable. This active high signal indicates DMA operations on the host
data bus.
I/O Address. These bits determine the I/O address to be accessed during IORJ
and IOWJ cycles.
DMA Acknowledge. An active low input signal acknowledging the request for a
DMA data transfer. This input enables the DMA read or write internally.
DMA request. This active high output is the DMA request for byte transfers of
data to the host. This signal is cleared on the last byte of the data transfer by
the DACKJ signal going low.
Terminal Count. This signal indicates to the M512x that data transfer is
complete. TC is only accepted when DACKJ is low. TC is active high in AT
mode and active low in PS/2 mode.
Interrupt Requests.
Reset. This active high signal resets the M512x and must be valid for 500 ns
minimum. In M512x, the falling edge of reset latches the jumper configuration.
The jumper select lines must be valid 50 ns prior to this edge.
Read Disk Data. This raw data read signal from the disk is connected here.
Each falling edge represents a flux transition of the encoded data.
Write Gate. This active-low, high-drive output enables the write circuitry of the
selected disk drive. This signal prevents glitches during power-up and power-
down. Unstable power prevents writing to the disk.
Write Data. This active low output is a write- precompensated serial data to be
written onto the selected disk drive. Each falling edge causes a flux change on
the media.
Head Select. This active low output determines which disk drive head is active.
Low = Head 0, high (open) = Head 1.
Direction. This active low output determines the direction of the head
movement (low = step-in, high = step-out). During write or read modes, this
output is high.
Step. This active low signal produces a pulse to move the head during a seek
operation.
Disk Change. This disk interface signal indicates when the disk drive door is
open. This signal is read from bit D7 of address xx7h.
07-02-1997 Document Number: 512xDS02.doc
Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, R.O.C. Tel: [phone] Fax: [phone]
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