M5123 Datasheet, PDF (39/121 Pages) List of Unclassifed Manufacturers – Mega I/O Controller with Plug & Play

Acer Laboratories Inc.
M512x : Mega I/O Controller with PnP
--Preliminary, Confidential, Proprietary--
4.3 Result Phase Status Registers
The result phase of a command contains bytes that hold status information. The format of these bytes are described in the
following sections. Do not confuse these register bytes with the main status register which is a read-only register that is always
available. The result phase status registers are read from the data register only during the result phase.
4.3.1 Status Register 0 (ST0)
Table 4-16
Status Register 0 Description
Bit
D7~D6
D5
D4
D3
D2
D1, D0
Description
Interrupt Code :
00 = Normal termination of command.
01 = Abnormal termination of command.
Command was executed, but not successfully completed.
10 = Invalid command issue. Command issued was not recognized as a valid command.
11 = Ready changed state during the polling mode.
Seek End: This bit is set after a seek or recalibrate command is completed by the controller. Used
during sense interrupt command.
Equipment Check: This bit is set after a recalibrate command track 0 signal failed to occur. Used
during sense interrupt command.
Not Used: 0
Head Number: At end of execution phase.
Drive Select: At end of execution phase.
00 = Drive 0 selected 01 = Drive 1 selected
10 = Drive 2 selected 11 = Drive 3 selected
4.3.2 Status Register 1 (ST1)
Table 4-17
Status Register 1 Description
Bit
D7
D6, D3
D5
D4
D2
D1
D0
Description
End of Track: This bit is set when the controller has transferred the last byte of the last sector
without the TC pin becoming active. The last sector is the end-of-track sector number programmed
in the command phase.
Not Used: 0
CRC Error: If this bit is set and bit 5 of ST2 is clear, then there was a CRC error in the address field
of the correct sector. If bit 5 of ST2 is set, then there was a CRC error in the data field.
Over Run: This bit is set when the controller was not serviced by the CPU soon enough during a
data transfer in the execution phase. Table 4-18 shows the time values.
No Data: This bit is set for any three possible problems:
1. Controller cannot find the sector specified in the command phase during the execution of a
read, write, or scan command. An address mark was found even if it is not a blank disk.
2. Controller cannot read any address fields without a CRC error during read ID command.
3. Controller cannot find the starting sector during execution of read a track command.
Not Writable: Set if the write protect pin is active when a write or format command is issued.
Missing Address Mark: If this bit is set and bit 0 of ST2 is clear then the disk controller cannot
detect any address field address mark after two disk revolutions. If bit 0 of ST2 is set, then the disk
controller cannot detect the data field address mark.
07-02-1997 Document Number: 512xDS02.doc
Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, R.O.C. Tel: [phone] Fax: [phone]
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