A40MX02 Datasheet, PDF (80/123 Pages) List of Unclassifed Manufacturers – 40MX and 42MX FPGA Families

40MX and 42MX FPGA Families
Table 39 •
A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, V_CCA = 3.0V, T_J = 70°C)
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Synchronous SRAM Operations (Continued)
t_ADH
Address/Data Hold Time
0.0
0.0
0.0
0.0
0.0
ns
t_RENSU
Read Enable Set-Up
0.9
1.0
1.1
1.3
1.8
ns
t_RENH
Read Enable Hold
4.8
5.3
6.0
7.0
9.8
ns
t_WENSU
Write Enable Set-Up
3.8
4.2
4.8
5.6
7.8
ns
t_WENH
Write Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
t_BENS
Block Enable Set-Up
3.9
4.3
4.9
5.7
8.0
ns
t_BENH
Block Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
Asynchronous SRAM Operations
t_RPD
t_RDADV
t_ADSU
t_ADH
t_RENSUA
Asynchronous Access Time
11.3
12.6
14.3
16.8
23.5 ns
Read Address Valid
12.3
13.7
15.5
18.2
25.5
ns
Address/Data Set-Up Time
2.3
2.5
2.8
3.4
4.8
ns
Address/Data Hold Time
0.0
0.0
0.0
0.0
0.0
ns
Read Enable Set-Up to Address 0.9
1.0
1.1
1.3
1.8
ns
Valid
t_RENHA
Read Enable Hold
t_WENSU
Write Enable Set-Up
t_WENH
Write Enable Hold
t_DOH
Data Out Hold Time
Input Module Propagation Delays
4.8
5.3
6.0
7.0
9.8
ns
3.8
4.2
4.8
5.6
7.8
ns
0.0
0.0
0.0
0.0
0.0
ns
1.8
2.0
2.1
2.5
3.5 ns
t_INPY
t_INGO
Input Data Pad-to-Y
Input Latch Gate-to-
Output
1.4
1.6
1.8
2.1
3.0 ns
2.0
2.2
2.5
2.9
4.1 ns
t_INH
Input Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
t_INSU
Input Latch Set-Up
0.7
0.7
0.8
1.0
1.4
ns
t_ILA
Latch Active Pulse Width
6.5
7.3
8.2
9.7
13.5
ns
Notes:
1. For dual-module macros, use t_PD1 + t_RD1 + t_PDn, t_CO + t_RD1 + t_PDn, or t_PD1 + t_RD1 + t_SUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-74
v6.0