A40MX02 Datasheet, PDF (121/123 Pages) List of Unclassifed Manufacturers – 40MX and 42MX FPGA Families

Datasheet Information
FPGA Families 40MX and 42MX
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous version
v5.1
Changes in current version (v 6. 0 )
Page
The "Ease of Integration" section was updated.
1-i
The "Temperature Grade Offerings" section is new.
1-iii
The "Speed Grade Offerings" section is new.
1-iii
The "General Description" section was updated.
1-1
The "MultiPlex I/O Modules" section was updated.
1-6
The "User Security" section was updated.
1-6
Table 1 • Voltage Support of MX Devices was updated.
1-7
The "Power Dissipation" section was updated.
1-8
The "Static Power Component" section was updated.
1-8
The "Equivalent Capacitance" section was updated.
1-8
Figure 1-13 • Silicon Explorer II Setup with 42MX was updated.
1-10
Table 4 • Supported BST Public Instructions was updated.
1-11
Figure 1-14 • 42MX IEEE 1149.1 Boundary Scan Circuitry was updated.
1-11
Table 5 • Boundary Scan Pin Configuration and Functionality was updated.
1-12
The "Development Tool Support" section was updated.
1-13
The Table 7 • Absolute Maximum Ratings for 42MX Devices* and the Table 6 • Absolute 1-14
Maximum Ratings for 40MX Devices* were updated.
The Table 9 • 5V TTL Electrical Specifications was updated.
1-15
The Table 13 • 3.3V LVTTL Electrical Specifications was updated.
1-17
In the "Mixed 5.0V/3.3V Electrical Specifications" section, Table 14 • Absolute Maximum 1-18
Ratings*, Table 15 • Recommended Operating Conditions, and Table 16 • Mixed 5.0V/3.3V
Electrical Specificationswere updated.
The Table 17 • DC Specification (5.0V PCI Signaling)¹ was updated.
1-19
The Table 19 • DC Specification (3.3V PCI Signaling)¹ was updated.
1-20
The <zBlue>Junction Temperature (T_J) section, "Package Thermal Characteristics" section, and the 1-22
tables were updated.
Figure 1-17 • 40MX Timing Model* was updated.
1-23
Figure 1-19 • 42MX Timing Model (Logic Functions Using Quadrant Clocks)
1-24
The Figure 1-20 • 42MX Timing Model (SRAM Functions) was updated.
1-24
The Figure 1-27 • Output Buffer Latches was updated.
1-27
The Table 22 • 42MX Temperature and Voltage Derating Factors is new.
1-31
The Table 23 • 40MX Temperature and Voltage Derating Factors is new.
1-32
The "Pin Descriptions" section was updated.
1-77
In the 100-Pin PQFP table, the following pins changed:
2-7
Pin 64 (42MX09 and 42MX16) has changed to LP
v6.0
3-1