A40MX02 Datasheet, PDF (35/123 Pages) List of Unclassifed Manufacturers – 40MX and 42MX FPGA Families

40MX and 42MX FPGA Families
RCLK
REN
t_CKHL
RDAD[5:0]
RD[7:0]
Note: Identical timing for falling edge clock.
Figure 1-31 • 42MX SRAM Synchronous Read Operation
t_RCKHL
t_RENSU
t_RENH
t_ADSU
Valid
t_DOH
Old Data
t_ADH
t_RCO
New Data
RDAD[5:0]
RD[7:0]
t _RDADV
ADDR1
ADDR2
t_DOH
t _RPD
Data 1
Data 2
Figure 1-32 • 42MX SRAM Asynchronous Read Operation—Type 1 (Read Address Controlled)
WEN
t_WENSU
t_WENH
WD[7:0]
WRAD[5:0]
BLKEN
WCLK
Valid
t_ADSU
t_ADH
t_RPD
t_DOH
RD[7:0]
Old Data
New Data
Figure 1-33 • 42MX SRAM Asynchronous Read Operation—Type 2 (Write Address Controlled)
v6.0
1-29