83C795 Datasheet, PDF (80/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

LAN CONTROLLER OVERVIEW
83C795
7.1.3 LAN Controller Internal Bus Arbitration
T his portion of the 83C795 is us ed to res olve
conflicts that can occur on databus es us edby both
the DMA controller and hos t acces s es to the
internal regis ters of the LAN Controller s ection.
T he LAN bus arbitration s ection obs erves a LAN
s elect (CS ) signal derived from the memory bus
arbiter and provides a ’ready’ hands hake s ignal in
return. It als o controls internal data flow within the
L AN contr ol l er and hol ds off the DMA
microcontroller during I/O acces s es .
7.1.4 DMA Microcontroller
T he core of the DMA controller is a R OM-bas ed
microcontroller which includes an addres s counter
for the memory pos ition, comparators for internal
address comparis ons , s omedecrementers for loop
control, regis ters for s torage of operatingvariables ,
and I/O control s ignals that attach to many circuits
within the LAN controller s ection of the chip.
In addition tothemicrocodeas s ociatedwith normal
trans mit, receive and loopback proces ses , there is
additional code to facilitate tes ting of the LAN
controller.
7.1.5 How to Access Registers
Arequest for LAN regis ter acces s is madewhen the
host presents an I/O addres s that decodes to a
regis ter within the upper 16 bytes of the 83C795’s
I/O block and a valid IOR or IOW is pres ented.
T he chip will res pond with an I/O Channel Not
R eady s ignal (IOR DY) while internal arbitration
proceeds . It remains NOT IOR DY until the des ired
trans fer is ready to be completed.
Acces s totheregis ters of theLAN controller s ection
is allowed after any ongoing DMA bur s t is
completed. At that time, the DMA may wis h to
become activeagain in res pons etonewneeds , but
thearbitration logicwill allowhos t acces s tothechip
until the I/O strobe becomes fals e. T he arbiter
generates the IOR DY s ignal as an indication to the
host that the internal bus has been made available
and that the reques ted I/O access has been made.
Between acces s es to the chip, IOR DY is undriven.
To readfromaregister, an I/O addres s is placedon
theS Axx pins andIOR is ass ertedby thehos t (mus t
be as s erted after a valid addres s ) and recognized
by the bus arbitration logicwhich enables dataflow
from the address ed regis ter to the D00-D07 pins .
R egis ter reads are always done through the
D00-D07 pins , except for 16-bit I/O pipe acces ses .
T he D08-D15 pins will be tri-stated during read
operations. IOR DY will indicate when the hos t may
s ample data and terminate the read operation.
To write to a register, an I/O addres s is placed on
the S Axx pins andIOW is ass erted by the hos t and
recogniz ed by the bus arbiter. Addres s mus t
become s table before IOW is as serted. When the
bus is free for the trans fer, IOR DY is as s erted. Data
is latched into an intermediate trans fer latch with
the trailingedge of IOW andthen trans ferredto the
destination regis ter two clocks later.
T his delayed write operation requires an internal
recovery period between hos t acces s es to
regis ters. T his periodis documentedin the detailed
timing diagrams .
7.1.6 Memory Interface
T he internal DMA controller moves packets
between buffer memory and the F IF Os .
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