83C795 Datasheet, PDF (43/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

83C795
ETHERNET SYSTEM CONTROLLER REGISTERS
5.2.17 NEXT - DMA Controller Next Buffer
Register
Normal Map R ead/Write Port = 2:15
T his is a working register of the DMA controller. It
holds a pointer to the next buffer to be opened.
BIT
7 A15
6 A14
5 A13
4 A12
3 A11
2 A10
1 A09
0 A08
NEXT
RESET
X
X
X
X
X
X
X
X
5.2.18 RADDH - Receive Burst Starting
Address High Register
Normal Map R ead/Write Port = 2:19
T his is the higher 8 bits of a register pair us ed
internally by theDMAcontroller as as cratch padfor
the burst addres s of the receive proces s. Writingto
the R ADDH and R ADDL r egi s ter s whi l e
communication is taking place may caus e errors in
the DMA proces s .
BIT
7 A15
6 A14
5 A13
4 A12
3 A11
2 A10
1 A09
0 A08
RADDH
RESET
X
X
X
X
X
X
X
X
5.2.19 RADDL - Receive Burst Starting
Address Low Register
Normal Map R ead/Write Port = 2:18
T his is the lower 8 bits of a register pair us ed
internally by theDMAcontroller as as cratch padfor
the burst addres s of the receive proces s. Writingto
the R ADDH and R ADDL r egi s ter s whi l e
communication is taking place may caus e errors in
the DMA proces s .
BIT
7 A07
6 A06
5 A05
4 A04
3 A03
2 A02
1 A01
0 A00
RADDL
RESET
X
X
X
X
X
X
X
X
5.2.20 RBEGIN - Receive Buffer Starting
Address Register
Linked-List Map R ead Port = 2:11 Linked-Lis t Map
Write Port = 0:11
T his register holds the upper 8 bits of the s tarting
address of the receive buffer des criptor table. T he
lower 8 bits are as sumed to be zero.
BIT
RBEGIN
7 RB15
6 RB14
5 RB13
4 RB12
3 RB11
2 RB10
1 RB09
0 RB08
RESET
X
X
X
X
X
X
X
X
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