83C795 Datasheet, PDF (53/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

83C795
ETHERNET SYSTEM CONTROLLER REGISTERS
5.2.48 RENH - Receive Enhancement Register
Normal Map R ead/Write Port = 0:19
T he R eceive E nhancement R egis ter contains
s everal bits requiredfor thenewreceive features of
the 83C795 chip.
BIT
7—
6—
5—
4—
3—
2 REMPTY
1 ERFBIT
0 WRAPEN
RENH
RESET
0
0
0
0
0
0
0
0
Bit 2: REMPTY, Ring Bit Empty
When R E MPT Y = 1, this read-only bit indicates that
the receive buffer ring has no completely received
frames .
Bit 1: ERFBIT, Early Receive Fail Bit
When E R F BIT = 1 it indicates that an underrun has
occurred during the reception of a frame. T he hos t
clears this bit after reading the addres s where the
failure occurred from the E R FA R egis ters.
Bit 0: WRAPEN, Automatic Ring-Wrap Enable
When WR APE N = 1 it enables the auto-wrapping
feature. F or more information on Automatic R ing-
Wrap, refer to page 87.
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