SI5020 Datasheet, PDF (8/18 Pages) List of Unclassifed Manufacturers – SiPHY MULTI-RATE SONET/SDH CLOCK AND DATA RECOVERY IC

Si5020
Table 4. AC Characteristics (PLL Characteristics)
(V_A 2.5 V ± 5%, T_A = –40°C to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Jitter Tolerance
(OC-48)*
J_{TOL(P–P)}
f = 600 Hz
f = 6000 Hz
40
TBD
—
4
TBD
—
f = 100 kHz
4
TBD
—
Jitter Tolerance (OC-12 Mode)^*
J_{TOL(P–P)}
f = 1 MHz
f = 30 Hz
f = 300 Hz
0.4 TBD
—
40
TBD
—
4
TBD
—
f = 25 kHz
4
TBD
—
Jitter Tolerance (OC-3 Mode)^*
J_{TOL(P–P)}
f = 250 kHz
f = 30 Hz
f = 300 Hz
0.4 TBD
—
60
TBD
—
6
TBD
—
f = 6.5 kHz
6
TBD
—
f = 65 kHz
0.6 TBD
—
Jitter Tolerance (Gigabit Ethernet) T_JT(P-P) IEEE 802.3z Clause 38.68 600
TBD
—
Receive Data Total Jitter
Tolerance
Jitter Tolerance (Gigabit Ethernet) D_JT(P-P) IEEE 802.3z Clause 38.69 370
TBD
—
Receive Data Deterministic Jitter
Tolerance
RMS Jitter Generation^*
J_GEN(rms) with no jitter on serial data —
3.0
5.0
Peak-to-Peak Jitter Generation^* J_GEN(rms) with no jitter on serial data
—
25
55
Jitter Transfer Bandwidth^*
J_BW
OC-48 Mode
—
—
2.0
OC-12 Mode
—
—
500
Jitter Transfer Peaking^*
Acquisition Time
OC-3 Mode
—
—
130
J_P
—
0.03
0.1
T_AQ
After falling edge of
1.45
1.5
1.7
PWRDN/CAL
From the return of valid
40
60
150
data
Input Reference Clock Duty Cycle C_DUTY
Reference Clock Range
40
50
60
19.44 — 168.75
Input Reference Clock Frequency
Tolerance
C_TOL
–100
—
100
Frequency Difference at which
LOL
Receive PLL goes out of Lock
(REFCLK compared to the divided
down VCO clock)
TBD 600 TBD
Frequency Difference at which
Receive PLL goes into Lock (REF-
CLK compared to the divided
down VCO clock)
LOCK
TBD 300 TBD
*Note: Bellcore specifications: GR-253-CORE, Issue 2, December 1995. Using PRBS 2²³ – 1 data pattern.
Unit
UIp-p
UIp-p
UIp-p
UIp-p
UIp-p
UIp-p
UIp-p
UIp-p
UIp-p
UIp-p
UIp-p
UIp-p
ps
ps
mUI
mUI
MHz
kHz
kHz
dB
ms
µs
%
MHz
ppm
ppm
ppm
8
Preliminary Rev. 0.8