SI5020 Datasheet, PDF (14/18 Pages) List of Unclassifed Manufacturers – SiPHY MULTI-RATE SONET/SDH CLOCK AND DATA RECOVERY IC

Si5020
Pin Descriptions: Si5020
Pin #
1
4, 5
6
9, 10
12, 13
20 19 18 17 16
REXT 1
15 ^PWRDN/CAL
VDD 2
GND 3
REFCLK+ 4
GND
Pad
14 VDD
13 DOUT+
12 DOUT–
REFCLK– 5
11 VDD
6 7 8 9 10
Top View
Figure 10. Si5020 Pin Configuration
Pin Name
REXT
REFCLK+,
REFCLK–
LOL
DIN+, DIN–
DOUT–,
DOUT+
Table 9. Si5020 Pin Descriptions
I/O Signal Level
Description
External Bias Resistor.
This resistor is used by onboard circuitry to estab-
lish bias currents within the device. This pin must
be connected to GND through a 10 kΩ (1%) resis-
tor.
I
See Table 2 Differential Reference Clock.
The reference clock sets the initial operating fre-
quency used by the onboard PLL for clock and data
recovery. Additionally, the reference clock is used to
derive the clock output when no data is present.
O
LVTTL Loss of Lock.
This output is driven high when the recovered clock
frequency deviates from the reference clock by the
amount specified in Table 4 on page 8.
I
See Table 2 Differential Data Input.
Clock and data are recovered from the differential
signal present on these pins.
O
CML
Differential Data Output.
The data output signal is a retimed version of the
data recovered from the signal present on DIN. It is
phase aligned with CLKOUT and is updated on the
rising edge of CLKOUT.
14
Preliminary Rev. 0.8