SI5020 Datasheet, PDF (15/18 Pages) List of Unclassifed Manufacturers – SiPHY MULTI-RATE SONET/SDH CLOCK AND DATA RECOVERY IC

Si5020
Table 9. Si5020 Pin Descriptions (Continued)
Pin #
Pin Name
I/O Signal Level
Description
15
PWRDN/CAL
I
LVTTL
Power Down.
To shut down the high-speed outputs and reduce
power consumption, hold this pin high. For normal
operation, hold this pin low.
Calibration.
To initiate an internal self-calibration, force a high-
to-low transition on this pin. (See "PLL Self-Calibra-
tion‚" on page 10.)
Note: This input has a weak internal pulldown.
16, 17
CLKOUT–,
O
CLKOUT+
CML
Differential Clock Output.
The output clock is recovered from the data signal
present on DIN. In the absence of data, the output
clock is derived from REFCLK.
19, 20
RATESEL1,
I
RATESEL0
2, 7, 11, 14
3, 8, 18, and
GND Pad
VDD
GND
LVTTL
2.5 V
GND
Data Rate Select.
These pins configure the onboard PLL for clock and
data recovery at one of four user selectable data
rates. See Table 7 for configuration settings.
Note: These inputs have weak internal pulldowns.
Supply Voltage.
Nominally 2.5 V.
Supply Ground.
Nominally 0.0 V. The GND pad found on the bottom
of the 20-pin micro leaded package (see Figure 11)
must be connected directly to supply ground.
Preliminary Rev. 0.8
15