PT7A4410 Datasheet, PDF (8/34 Pages) List of Unclassifed Manufacturers – T1/E1/OC3 System Synchronizer

Data Sheet
PT7A4410/4410L
T1/E1/OC3 System Synchronizer
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Whenever there is a change in the input reference source, such
as a switch from the primary reference signal (PRI) to second-
ary reference signal (SEC), the typical result is a step change in
phase of the DPLL input signal that causes an unacceptable
step change in the DPLL input signal phase. The TIE Correc-
tor circuit is used to eliminate the step change in the DPLL
input signal phase, thus maintaining continuity of phase at
the DPLL output.
Referring to Figure 3, the selected reference signal (e.g. SEC)
feeds the Comparing Circuit where it is compared with the
feedback signal from the output circuit. Whenever there is a
step change in the reference input signal’s phase, the Compar-
ing Circuit will generates a Delay Value for the Programmable
Delay Circuit. The Delay Circuit then delays the input refer-
ence signal by the Delay Value, thus providing the DPLL with
a Virtual Reference Signal having no phase discontinuity.
The DPLL phase detects and tracks the Virtual Reference Sig-
nal. As the Virtual Reference Signal exhibits no discontinuity
of phase, there is no phase transient in the DPLL output signal.
This is the Normal operation of the device.
As the Programmable Delay Circuit maintains the phase of the
Virtual Reference Signal while the TIE Corrector is enabled,
there will in general be a time delay between the chip output
signals and the selected input reference signal after switching
to a new input reference source (e.g. from PRI to SEC). Each
time a new reference source is selected, there will in general be
a new time delay. The value of this delay represents the accu-
mulation of the phase errors measured and corrected for during
the various reference source switching events.
The Programmable Delay Circuit can be zeroed through the
TCLR pin (low level, min. duration 300ns), realigning the
output signals with the present input reference signal. The
speed of realignments is limited by the Limiter in the DPLL to
5ns per 125µs. Convergence is in the direction of least phase
travel.
Digital Phase-Locked Loop (DPLL)
The DPLL consists of the Phase Detector, Limiter, Loop Filter,
Digitally Controlled Oscillator (DCO) and Control Circuit.
See Figure 4 for the block diagram of DPLL.
During the input reference signals source switching process, a
holdover state will occurr before the DPLL begins to track the
Virtual Reference Signal. When the input reference is switched
to the new source, the State Machine initiates Holdover State,
during which the DPLL does not use the Virtual Reference
Signal. Instead, it uses stored information to produce a clock
signal that is compared in the Comparing Circuit with the
Feedback Signal. This compared result is sent to the Program-
mable Delay Circuit which in turn delivers to the DPLL input
a new Virtual Reference Signal whose phase is aligned with
that of the previous input reference signal. The State Machine
then terminates Holdover State and return the device to Nor-
mal state.
Figure 4. Block Diagram of DPLL
The Virtual Reference Signal from TIE is sent to Phase Detec-
tor for comparison with the Feedback Signal from the Feed-
back Frequency Select MUX. An error signal corresponding to
their instantaneous phase difference is produced and sent to
the Limiter.
The Limiter amplifies this error signal to ensure the DPLL
responds to all input transient conditions with a maximum
output phase slope of 5ns per 125µs. This performance easily
meets the maximum phase slope of 7.6ns per 125µs or 81ns per
1.326ms specified by AT&T TR62411.
The Loop Filter is a 1.9Hz low pass filter for all three reference
frequency selections: 8kHz, 1.544MHz and 2.048MHz. The
filter ensures that the jitter transfer requirements in ETS 300-
011 and AT&T TR62411 are met.
Virtual
Reference
from TIE
Corrector
Phase
Detector
Limiter
Loop
Filter
Control Circuit
DCO
DPLL Reference
to
Output Interface
Circuit
PT0106(09/02)
Feedback Signal
From
Frequency Select MUX
State Select From
Input Impairment
Monitor
State Select
From
State Machine
8
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