PT7A4410 Datasheet, PDF(17/34 Page) List of Unclassifed Manufacturers

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Data Sheet

PT7A4410/4410L

T1/E1/OC3 System Synchronizer

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JT1o

JT1i

(

-A

)

(

-18

)

2.5UI

J = J x ( 1UIT1) = J x ( 644ns ) = 3.3UI

E1o T1o 1UIE1 T1o 488ns

Using the above method, the jitter attenuation can be calcu-

lated for all combinations of inputs and outputs based on the

three jitter transfer functions provided.

Capture Range: The PT7A4410/4410L DPLL is not at present

in a state of synchronization (lock) with the incoming reference

signal, it is able to initiate (acquire) lock only if the signalâs fre-

quency is within a certain range, called the Capture Range. For

any PLL, no portion of the Capture Range can fall outside the

Lock Range, and, in general, the Capture Range is more narrow

than the Lock Range. However, owing to the design of its Phase

Detector, the PT7A4410/4410Lâs Capture Range is equal to its

Lock Range.

Note that the resulting jitter transfer functions for all combina-

tions of inputs (8kHz, 1.544MHz, 2.048MHz) and outputs

(8kHz, 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz,

16.384MHz, 6.312MHz, 19.44MHz) for a given input signal

(jitter frequency and jitter amplitude) are the same.

Since intrinsic jitter is always present, jitter attenuation will

appear to be lower for small input jitter signals than for large

ones. Consequently, accurate jitter transfer function measure-

ments are usually made with large input jitter signals (e.g.,

75% of the specified maximum jitter tolerance).

Frequency Accuracy: Frequency accuracy is defined as the

absolute tolerance of an output clock signal when it is not

locked to an external reference, but is operating in a free run-

ning mode. For the PT7A4410/4410L, the Free-Run accuracy

is equal to the Master Clock (OSCi) accuracy.

Holdover Accuracy: Holdover accuracy is defined as the ab-

solute tolerance of an output clock signal, when it is not locked

to an external reference signal, but is operating using storage

techniques. For the PT7A4410/4410L the storage value is de-

termined while the device is in Normal State and locked to an

external reference signal. The absolute Master Clock (OSCi)

accuracy of the PT7A4410/4410L does not affect Holdover

accuracy, but the change in OSCi accuracy while in Holdover

Mode does.

Lock Range: If the PT7A4410/4410L DPLL is already in a

state of synchronization (âlockâ) with the incoming reference

signal, it is able to track this signal to maintain lock as its

frequency varies over a certain range, called the Lock Range.

The size of Lock Range is related to the range of the Digitally

Controlled Oscillators and is equal to 230ppm minus the ac-

curacy of the master clock (OSCi). For example, a 32ppm mas-

ter clock results in a Lock Range of 198ppm.

Phase Slope: Phase slope is measured in seconds per second

and is the rate at which a given signal changes phase with

respect to an ideal signal of constant frequency. The given

signal is typically the output signal. The ideal signal is of

constant frequency and is nominally equal to the value of the

final output signal or final input signal.

Time Interval Error (TIE): TIE is the time delay between a

given timing signal and an ideal timing signal.

Maximum Time Interval Error (MTIE): MTIE is the maxi-

mum peak to peak delay between a given timing signal and an

ideal timing signal within a particular observation period.

MTIE(S) = TIEmax(t) - TIEmin(t)

Phase Continuity: Phase continuity is the phase difference

between a given timing signal and an ideal timing signal at

the end of a particular observation period. Usually, the given

timing signal and the ideal timing signal are of the same fre-

quency. Phase continuity applies to the output of the synchro-

nizer after a signal disturbance due to a reference source switch

or a state change. The observation period is usually the time

from the disturbance, to just after the synchronizer has settled

to a steady state.

For the PT7A4410/4410L, the output signal phase continuity

is maintained to within 5ns at the instance (over one frame) of

all reference source switches and all state changes. The total

phase shift, depending on the switch or type of state change,

may accumulate up to 200ns over many frames. The rate of

change of the 200ns phase shift is limited to a maximum phase

slope of approximately 5ns/125Âµs. This meets the AT&T

TR62411 maximum phase slope requirement of 7.6ns/125Âµs

(81ns/1.326ms).

PT0106(09/02)

Ver:0

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