PD5019 Datasheet, PDF (8/14 Pages) List of Unclassifed Manufacturers – Telephone Ring Generator Controller

FREQUENCY SELECTION
F0, F1: Selection of a single output ringing frequency between the
four available options of 16.7, 20, 25 or 50Hz is achieved by the F0
and F1 inputs.
The state of F0 and F1 inputs must be set and stable prior to
powering the PD5019. Changing the input state while the
PD5019 is operating may not effect the output frequency, and
may cause the controller to become unstable state.
The frequency selection should be made according to the OUTPUT
RINGING & PWM FREQUENCIES table on page 45.
These inputs are CMOS standard and can be driven directly from
CMOS components, or the frequency selection can be achieved by
tying them to GND or Vcc.
Note: The PD5019 operation may be affected by excessive noise
surges on F0 and F1 terminals while operating.
VCC
F1 3
100K
VCC
100K
F0 4
PD5019
TELEPHONE RING GENERATOR CONTROLLER
CAD_In: This input line should be connected to the output of the A/D
circuit’s external comparator. CAD_In = “1” will increase the PWM
duty cycle at the PAD_Out line. CAD_In = “0” will decrease the PWM
duty cycle at the PAD_Out line. When the sampled voltage is stable,
the A/D PWM duty cycle will change up and down by 1 bit and the
comparator output will vibrate. These 1-bit vibrations are ignored by
the A/D.
Applications that use highly regulated power supplies may eliminate
the A/D external portions. In this event, the CAD_In should be
permanently connected to GND. Note that no output voltage
regulations based on input voltage changes will be performed.
LOW PASS NETWORK
The network is connected between the PAD_Out and the negative
input of the comparator, built from R3 & C1.
The low pass network is designed to average the PWM signal into a
DC Level. This DC level is compared to the sampled voltage.
It is recommended to calculate the Low Pass network components
values according to the following:
τ(Recommended) = C1 • R3 = 89.1µS @ 96KHz Operation
τ(Recommended) = C1 • R3 = 52µS @ 307KHz Operation
* For timing details refer to A/D CONVERTER, INTERNAL
FUNCTIONAL PARAMETERS TABLE.
Vin
Frequency Selection Inputs
LINE REGULATION (A/D UNIT)
The ring generator circuit design is based on an open loop flyback
topology. In order to regulate the output for input voltage changes, a
forward compensation mechanism is used.
This mechanism is based on a digital sampling of the input voltage
by the A/D unit, and correction of the main PWM duty cycle
according to the internal transfer function.
The input voltage is sampled by an 8bit A/D unit, which is composed
of external analog components and the internal PD5019 logic.
The internal portion of the A/D generates a PWM signal (PAD_Out)
with a changing duty cycle according to the voltage sampled by the
CAD_In terminal.
The sampled input voltage information influences the ringer output
voltage amplitude in such a way that changes in Vin generates only a
small change in Vout.
PAD_Out: PWM output for the external A/D circuit. The PWM
frequency is the oscillator frequency divided by 8.
This line is connected to an external Low pass network that averages
the PWM pulses to a DC voltage. The level of this DC voltage is
proportional to the duty cycle of the PWM signal. The Low pass
network is connected to the negative input of an external comparator.
This DC voltage tracks the sampled voltage that is connected to the
positive input of the comparator. If the DC voltage is lower than the
sampled voltage, the internal A/D circuit will increase the PWM duty
cycle. This will increase the DC level. The opposite happens when
the sampled voltage is lower than the DC voltage.
R1
Vsample
R2
3
+
2_-
C1
PD5019
1
CMP_IN
R3
PAD_OUT
INTERNAL
A/D
8Bit Data to Transfer
Function
A/D Circuit Implementation
♦ The comparator inputs for the A/D function must operate in the
range of 0 to 5V.
♦ The Vsample sampling is synchronized for the sine wave peak.
Voltage Divider: The voltage divider connects to the positive input of
the comparator and is built of R1 & R2.
The voltage divider is required when an input voltage, Vin, higher
than 5V is used. Design the Vsample voltage divider to deliver 2.5V
for typical Vin Value is recommended.
OUTPUT PROTECTION MECHANISM
The overload and short circuit protection mechanisms support three
protection levels:
1. Immediate pulse by pulse, input current limiting.
2. Power reduction, by output amplitude reduction.
3. Shut down for limited periods, to reduce heat dissipation.
The input of the protection unit is the CL input, connected to external
current sense circuit output.
CL - Current Limiting Pulse Counter:
When the CL input changes to a Low due to excessive switch
current, the PWM output immediately changes to Low until the end of
the current PWM cycle. This will terminate the current through the
switching FET and the CL input will return to a high level.
PowerDsine Ltd.
PowerDsine, Inc.
PowerDsine Europe
Tel: [phone] • Fax: [phone] • Email: [e-mail]
Tel: [phone] • Fax: [phone] • Email: [e-mail]
Tel: [phone] • Fax: [phone] • Email: [e-mail]