NT256S64V8HC0G Datasheet, PDF (8/10 Pages) List of Unclassifed Manufacturers – 32Mx64 bit Two Bank Unbuffered SDRAM Module

NT256S64V8HC0G
256MB : 32M x 64
Unbuffered SDRAM Module
AC Timing Parameters
Clock and Clock Enable Parameters
Symbol
Parameter
- 7K
- 75B
- 8B
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Note
tCK3
Clock Cycle Time, CAS Latency = 3
7
1000
7.5
1000
8
1000
ns
tCK2
Clock Cycle Time, CAS Latency = 2
7.5
1000
10
1000
10
1000
ns
tAC3(B) Clock Access Time, CAS Latency = 3
-
5.4
-
5.4
-
6
ns
1
tAC2(B) Clock Access Time, CAS Latency = 2
-
5.4
-
6
-
6
ns
1
tCKH
Clock High Pulse Width
2.5
-
2.5
-
3
-
ns
2
tCKL
Clock Low Pulse Width
2.5
-
2.5
-
3
-
ns
2
tCES
Clock Enable Set-up Time
1.5
-
1.5
-
2
-
ns
tCEH
Clock Enable Hold Time
0.8
-
0.8
-
1
-
ns
tSB
Power down mode Entry Time
0
7.5
0
7.5
0
12
ns
tT
Transition Time (Rise and Fall)
0.5
10
0.5
10
0.5
10
ns
1. Access time is measured at 1.4V. In AC Characteristics section, see notes.
2. t CKH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min). t CKL is the pulse width of
CLK measured from the negative edge to the positive edge referenced to VIL (max).
Common Parameters
Symbol
Parameter
- 7K
- 75B
- 8B
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Note
tCS
Command Setup Time
1.5
-
1.5
-
2
-
ns
tCH
Command Hold Time
0.8
-
0.8
-
1
-
ns
tAS
Address and Bank Select Set-up Time
1.5
-
1.5
-
2
-
ns
tAH
Address and Bank Select Hold Time
0.8
-
0.8
-
1
-
ns
tRCD
RAS to CAS Delay
20
-
20
-
20
-
ns
1
tRC
Bank Cycle Time
60
-
67.5
-
70
-
ns
1
tRFC
Auto Refresh to Active/Auto Refresh
60
-
67.5
-
70
-
tRAS
Active Command Period
45
100K
45
100K
50
100K
ns
1
tRP
Precharge Time
20
-
20
-
20
-
ns
1
tRRD
Bank to Bank Delay Time
15
-
15
-
20
-
ns
1
tCCD
CAS to CAS Delay Time
1
-
1
-
1
-
CLK
1.These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the num
ber of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Mode Register Set Cycle
Symbol
Parameter
- 7K
- 75B
- 8B
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Note
tRSC
Mode Register Set Cycle Time
2
-
2
-
2
-
CLK
1
1.These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the num
ber of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Preliminary 10 / 2001
8
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