NT256S64V8HC0G Datasheet, PDF (6/10 Pages) List of Unclassifed Manufacturers – 32Mx64 bit Two Bank Unbuffered SDRAM Module

NT256S64V8HC0G
256MB : 32M x 64
Unbuffered SDRAM Module
Operating, Standby, and Refresh Currents (T A =0 to 70 °C , V DD =3.3 ± 0.3V)
Parameter
Symbol
Test condition
Operating current
I_CC1
Precharge
standby current
in power-down mode
I_CC2P
I_CC2PS
Precharge
standby current in non
power-down mode
ICC2N
ICC2NS
No Operating current
( Active state : 4 bank)
ICC3P
ICC3N
Operating current
( Burst mode )
I_CC4
Auto(CBR)
refresh current
I_CC5
Self refresh current
I_CC6
Serial PD Device
I_SB
Standby Current
1 bank operation , tRC = tRC(mim), tCK = min
Active-Precharge Command cycling
without burst operation
CKE0 ≤ VIL (max), tCK = min,
S0 , S2 = V_IH (min)
CKE0 ≤ VIL (max), tCK =oo,
S0 , S2 = V_IH (min)
CKE0 ≥ VIH (min), tCK = min
S0 , S2 = V_IH (min)
CKE0 ≥ VIH (min), tCK =oo,
S0 , S2 = V_IH (min)
CKE0 ≤ VIL (max), tCK =min.
S0 , S2 = V_IH (min) (Power Down Mode)
CKE0 ≥ VIH (min), tCK =min
S0 , S2 = V_IH (min)
tCK =min , Read/ Write command cycling,
Multiple banks active, gapless data, BL=4
t_CK =min, CBR command cycling
CKE0 ≤ 0.2V
V_IN = GND or V_DD
Speed
Unit
- 7K - 75B - 8B
1200 1080 1080
mA
32
32
32
mA
32
32
32
mA
800
720
720
mA
144
144
144
mA
144
144
144
mA
960
800
800
mA
1560 1360 1360
mA
2000 1920 1920
mA
32
32
32
mA
30
30
30
µA
Serial PD Device Active
Power Supply Current
ICCA
SCL Clock Frequency=100 MHz
1
1
1
µA
1. The specified values are for one DIMM bank in the specified mode, and the other DIMM bank in Active Standby (I CC3N ).
2. The specified values are for both DIMM banks operating in the specified mode.
3. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t CK and t RC .
Input signals are changed up to three times during t RC (min).
4. The specified values are obtained with the output open.
5. Input signals are changed once during three clock cycles.
6. Input signals are stable.
7. Active Standby current will be higher if clock suspend is entered during a Burst Read cycle (add 1mA per DQ).
8. Input signals are changed once during t CK(min) .
9. VDD =3.3V.
10. As follows:
• Input pulse levels V DD x 0.1 to V DD x 0.9
• Input rise and fall times 10ns
• Input and output timing levels V DD x 0.5
• Output load 1 TTL gate and CL=100pF
Note
1, 3,4
2
2
2,5
2,6
2,7
2,5
1,4,8
1
2
9
10
Preliminary 10 / 2001
6
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.