NT256S64V8HC0G Datasheet, PDF (1/10 Pages) List of Unclassifed Manufacturers – 32Mx64 bit Two Bank Unbuffered SDRAM Module

NT256S64V8HC0G
256MB : 32M x 64
Unbuffered SDRAM Module
32Mx64 bit Two Bank Unbuffered SDRAM Module
based on 16Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD
Features
l 168-Pin Unbuffered 8-Byte Dual In-Line Memory Module
l Intended for PC133 applications
- Clock Frequency: 133MHz
- Clock Cycle: 7.5ns
- Clock Assess Time: 5.4ns
l Inputs and outputs are LVTTL (3.3V) compatible
l Single 3.3V ± 0.3V Power Supply
l Single Pulsed RAS interface
l SDRAMs have 4 internal banks
l Module has 2 physical bank
l Fully Synchronous to positive Clock Edge
l Data Mask for Byte Read/Write control
l Auto Refresh (CBR) and Self Refresh
l Automatic and controlled Precharge commands
l Programmable Operation:
- CAS Latency: 2, 3
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, 8
- Operation: Burst Read and Write or Multiple Burst Read with
Single Write
l Suspend Mode and Power Down Mode
l 4096 Refresh cycles distributed across 64ms
l Gold contacts
l SDRAMs in TSOP Type II Package
l Serial Presence Detect with Write Protect
Description
NT256S64V8HC0G is unbuffered 168-pin Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which is organized as 32Mx64
high-speed memory arrays and is configured as two 16M x 64 physical bank. The DIMM uses sixteen 16Mx8 SDRAMs in 400mil TSOP II
pack-ages. The DIMM achieves high-speed data transfer rates of up to 133MHz by employing a prefetch / pipeline hybrid architecture that
supports the JEDEC 1N rule while allowing very low burst power.
All control, address, and data input/output circuits are synchronized with the positive edge of the externally supplied clock inputs.
All inputs are sampled at the positive edge of each externally supplied clock (CK0 - CK3). Internal operating modes are defined by combinations
of RAS , CAS , WE , S0 - S3 , DQMB, and CKE0 – CKE1 signals. A command decoder initiates the necessary timings for each operation. A
14-bit address bus accepts address information in a row / column multiplexing arrangement.
Prior to any Access operation, the CAS latency, burst type, burst length, and Burst operation type must be programmed into the DIMM by
address inputs A0-A9 during the Mode Register Set cycle. The DIMM uses serial presence detects implemented via a serial EEPROM using
the two-pin IIC protocol. The first 128 bytes of serial PD data are used by the DIMM manufacturer. The last 128 bytes are available to the
customer.
Ordering Information
Part Number
NT256S64V8HC0G-7K
NT256S64V8HC0G-75B
NT256S64V8HC0G-8B
* CL = CAS Latency
MHz.
143MHz
133MHz
133MHz
100MHz
125MHz
100MHz
Speed
CL t RCD t RP
3
3
3
2
2
2
3
3
3
2
2
2
3
3
3
2
2
2
Organization
32Mx64
Leads
Gold
Power
3.3V
Preliminary 10 / 2001
1
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.