ARM946E-S Datasheet, PDF (8/218 Pages) List of Unclassifed Manufacturers – TECHNICAL REFERENCE MANUAL

Table 2-22
Table 2-23
Table 2-24
Table 2-25
Table 2-26
Table 2-27
Table 2-28
Table 2-29
Table 2-30
Table 2-31
Table 3-1
Table 3-2
Table 3-3
Table 4-1
Table 4-2
Table 6-1
Table 6-2
Table 7-1
Table 8-1
Table 8-2
Table 8-3
Table 8-4
Table 8-5
Table 8-6
Table 8-7
Table 8-8
Table 10-1
Table 10-2
Table A-1
Table B-1
Table B-2
Table B-3
Table B-4
Table B-5
Table B-6
Table B-7
Table B-8
Table B-9
TCM region/base size register format ........................................ 2-26
Tightly-coupled memory area size encoding .............................. 2-27
Register 15, BIST instructions .................................................... 2-29
Register 15, implementation-specific BIST instructions ............. 2-29
RAM BIST control register bit definitions .................................... 2-30
Test state register bit assignments ............................................. 2-31
Additional operations .................................................................. 2-32
Index fields for supported cache sizes ....................................... 2-34
Trace control register ................................................................. 2-34
Trace control register bit assignments ....................................... 2-35
TAG and index fields for supported cache sizes .......................... 3-4
Meaning of Cd bit values .............................................................. 3-9
Calculating index addresses ...................................................... 3-11
Protection register format ............................................................. 4-3
Region size encoding ................................................................... 4-4
Supported burst types .................................................................. 6-4
Data write modes ....................................................................... 6-13
Handshake encoding .................................................................... 7-7
Public instructions ...................................................................... 8-10
ARM946E-S (Rev 1) scan chain allocations .............................. 8-13
Scan chain 1 bits ........................................................................ 8-14
Scan chain 15 addressing mode bit order .................................. 8-15
Mapping of scan chain 15 address field to CP15 registers ........ 8-15
Status bit mapping of scan chain 15 address field
to CP15 registers ........................................................................ 8-17
Correlation between status bits and cache operations ............... 8-18
Coprocessor 14 register map ..................................................... 8-31
Instruction BIST address and general registers ......................... 10-7
Data BIST address and general registers .................................. 10-7
Timing parameter definitions ...................................................... A-12
Clock interface signals ................................................................. B-3
TCM interface signals ................................................................... B-4
AHB signals .................................................................................. B-5
Coprocessor interface signals ...................................................... B-7
Debug signals ............................................................................... B-9
JTAG signals .............................................................................. B-11
Miscellaneous signals ................................................................ B-12
ETM interface signals ................................................................. B-13
INTEST wrapper signals ............................................................ B-15
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