ARM946E-S Datasheet, PDF (75/218 Pages) List of Unclassifed Manufacturers – TECHNICAL REFERENCE MANUAL

Protection Unit
4.2 Memory regions
You can partition the address space into a maximum of eight regions. Each region is
specified by the following:
• region base address
• region size
• cache and write buffer configuration
• read and write access permissions.
The ARM architecture uses constants known as inline literals to perform address
calculations. These constants are automatically generated by the assembler and
compiler and are stored inline with the instruction code. To ensure correct operation,
you must define an area of memory, from where code is to be executed, that allows both
data and instruction accesses.
The base address and size properties are programmed using CP15 register 6. The format
for this is shown in Table 4-1.
Table 4-1 Protection register format
Register bits Function
31:12
11:6
5:1
0
Region base address
Unused
Region size
Region enable
Reset to disable (0).
4.2.1
Region base address
The base address defines the start of the memory region. You must align this to a
region-sized boundary. For example, if a region size of 8KB is programmed for a given
region, the base address must be a multiple of 8KB.
Note
If the region is not aligned correctly, this results in unpredictable behavior.
ARM DDI 0201A
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