ARM946E-S Datasheet, PDF (141/218 Pages) List of Unclassifed Manufacturers – TECHNICAL REFERENCE MANUAL

Debug Support
8.4.3
Scan chain 3
This scan chain allows ARM946E-S (Rev 1) macrocell to control an optional external
boundary scan chain. You can determine the length of scan chain 3.
8.4.4
Scan chain 15
Scan chain 15 allows debug access to the CP15 register bank and allows the cache to be
interrogated. Scan chain 15 is 39 bits long.
The order of scan chain 15 from the DBGTDI input to the DBGTDO output is shown
in Table 8-4.
Table 8-4 Scan chain 15 addressing mode bit order
Bits
38
37:32
31:0
Contents
Read = 0, write = 1
CP15 register address
CP15 data value
The mapping of the CP15 register address field of scan chain 15 to CP15 registers is
shown in Table 8-5.
Table 8-5 Mapping of scan chain 15 address field to CP15 registers
Address
Register
[37]
[36:33] [32] Number Name
Type
0
0000
0
C0.ID
ID register
Read
0
0000
1
C0.C
Cache type
Read
0
0001
0
C1
Control
Read/write
0
0010
0
C2.D
Data cachable bits
Read/write
0
0010
1
C2.I
Instruction cachable bits
Read/write
0
0011
0
C3
Write buffer control
Read/write
0
0100
0
C0.M
Tightly-coupled memory size
Read
0
0101
0
C5.D
Data space access permissions
Read/write
0
0101
1
C5.I
Instruction address access permissions
Read/write
ARM DDI 0201A
Copyright © 2001 ARM Limited. All rights reserved.
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