ACD80800 Datasheet, PDF (8/19 Pages) List of Unclassifed Manufacturers – Address Resolution Logic (8K MAC Addresses)

5. INTERFACE DESCRIPTION
Switch Interface
Switch interface provides a communication channel
between ACD’s switch controller chip and ACD80800.
As a frame is being received by ACD’s switch control-
ler chip , the destination address and source address
of the frame are snooped from the SWDIx lines of
ACD80800, with respect to the SWCLK signal.
ACD80800 carries a lookup process for each destina-
tion address, and a learning process for each source
address. The result of the lookup is returned to the switch
controller chip through the SWDOx lines. Table 1 shows
the associated signals in the Switch Interface.
• 0000 - Third to Last word
• 0001 - First word
• 0010 - Second word
• 0011 - Reserved
• 0100 - Reserved
• 0101 - Drop event
• 0110 - Jabber
• 0111 - False carrier
• 1000 - Alignment error
• 1001 - Flow control/collision^*
• 1010 - Short event/excessive collision^*
• 1011 - Runt/Late collision^*
• 1100 - Symbol error
• 1101 - FCS error
• 1110 - Long event
• 1111 - Reserved
Table-1: Switch Interface
Name Type
Description
SWDI0 ~
SWDI63
I
Input data, which can be 48-
bit or 64-bit wide
SWSTAT0 ~
SWSTAT3 ^I
Input data state
SWEOF
I End of frame indication signal
SWDIR0 ~
SWDIR1
I
Data direction indication
signal
SWSYNC I Port synchronization signal
SWPID0 ~
SWPID4
I
Port-ID indication signal
SWCLK
I
Reference clock
SWDOV O
Output data valid signal
SWDO0 ~
SWDO3
O
Output data which can be 2-
bit or 4-bit wide
The SWDIx signal comes from the SRAM Data bus of
ACD’s switch controller chip . Since all data of the re-
ceived frames have to be written into the shared memory
through the Data bus, the bus can be monitored for
occurrence of DA and SA values, indicated by the as-
sociated state bits. The signals in SWDIx bus can be a
48-bit or 64-bit wide data bus. For a 48-bit wide bus,
the first word will be the DA and the second word will be
the SA. For a 64-bit wide bus, DA is the first 48-bit of
first word, SA is the last 16-bit of first word plus first 32-
bit of second word.
SWDIR is a 2-bit signal to indicate the direction of the
data displayed on the SWDI bus, 01 for receiving, 10
for transmitting, 00 or 11 for other states. ACD80800
only deals with the received data.
SWSTAT bus is a 4-bit signal, used to indicate the mean-
ing (status) of the data. The 4-bit status is defined as:
*_{Note: error type depends on SWDIR is 01 or}
10.
SWSYNC is used to indicate port 0 is driving the Data
bus. It is used when the bus is evenly allocated in a time
division multiplexing manner, such that a monitoring de-
vice can implement a counter to indicate the ID of the
port which is driving the SWDI bus, and use SWSYNC
signal to reset the counter. When SWSYNC is in use,
SWPID is ignored.
SWPID is used to indicate the ID of the port which is
driving the Data bus. When SWPID is in use, SWSYNC
is ignored.
SWEOF is used to indicate the start and end of a frame.
It is always asserted when the corresponding port is
idling. The start of a frame is indicated by a high-to-low
transition of SWEOF signal. The end of a frame is indi-
cated by a low to high transition of SWEOF signal.
SWCLK is used to provide timing reference of input
data snooping and output data latching. The signal is
also used as the system clock of the chip.
SWDOV is used to indicate the start of a lookup result
package.
SWDOx is used to return the result of lookup to ACD’s
switch controller chip. Data is latched onto SWDOx bus
with respect to the rising edge of SWCLK signal. Each
result package is consisted by 5-bit source port ID, 2-
bit result, and 5-bit destination port ID. The 2-bit result
field is defined as 01 for match, with the port ID shown
by the 5-bit destination port ID field; 10 for no match;
11 for forced disregard (filtering).
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