24C128 Datasheet, PDF (6/8 Pages) Integrated Silicon Solution, Inc – 131,072-bit 2-WIRE SERIAL CMOS EEPROM

Turbo IC, Inc.
24C128/24C256
PRODUCT PRELIMINARY
CURRENT ADDRESS READ:
The internal memory address counter of the Turbo IC 24C128/
24C256 contains the last memory address accessed during
the previous read or write operation, incremented by one. To
start the current address read operation, the master issues
a start condition, followed by the device address byte 1010
(A2) (A1) (A0) 1. The Turbo IC 24C128/24C256 responds
with an acknowledge by pulling the SDA bus low, and then
serially shifts out the data byte accessed from memory at
the location corresponding to the memory address counter.
The master does not acknowledge, then sends a stop condi-
tion to terminate the read operation. It is noted that the
memory address counter is incremented by one after the
data byte is shifted out.
RANDOM ADDRESS READ:
The master starts with a dummy write operation (one with no
data bytes) to load the internal memory address counter by
first issuing a start condition, followed by the device address
byte 1010 (A2) (A1) (A0) 0, followed by the 2 memory ad-
dress bytes. Following the acknowledge from the Turbo IC
24C128/24C256, the master starts the current read opera-
tion by issuing a start condition, followed by the device ad-
dress byte 1010 (A2) (A1) (A0) 1. The Turbo IC 24C128/
24C256 responds with
an acknowledge by pulling the SDA bus low, and then seri-
ally shifts out the data byte accessed from memory at the
location corresponding to the memory address counter. The
master does not acknowledge, then sends a stop condition
to terminate the read operation. It is noted that the memory
address counter is incremented by one after the data byte is
shifted out.
SEQUENTIAL READ:
The sequential read is initiated by either a current address
read or random address read. After the Turbo IC 24C128/
24C256 serially shifts out the first data byte, the master ac-
knowledges by pulling the SDA bus low, indicating that it re-
quires additional data bytes. After the data byte is shifted
out, the Turbo IC 24C128/24C256 increments the memory
address counter by one. Then the Turbo IC 24C128/24C256
shifts out the next data byte. The sequential reads continues
for as long as the master keeps acknowledging. When the
memory address counter is at the last memory location, the
counter will ‘roll-over’ when incremented by one to the first
location in memory (address zero). The master terminates
the sequential read operation by not acknowledging, then
sends a stop condition.
Current Address Read
SDA LINE
S
T
R
A
E
R DEVICE A
T _ADDRESS D
M
L RA
S
S /C
B
B WK
S
T
O
DATA
P
M
N
S
O
B
A
C
K
Random Read
S
W
S
T
R
A
I
R DEVICE T
T _ADDRESS E
WORD
ADDRESS N
//
T
R
A
E
R DEVICE
A
T ADDRESS _D
SDA LINE
*!
//
M
L RA
A
A
S
S /C
C
C
B
B WK
K
K
DUMMY WRITE
S
T
O
DATA n
P
N
O
A
C
K
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