24C128 Datasheet, PDF (4/8 Pages) Integrated Silicon Solution, Inc – 131,072-bit 2-WIRE SERIAL CMOS EEPROM

Turbo IC, Inc.
24C128/24C256
PRODUCT PRELIMINARY
DEVICE ADDRESSING:
Following the start condition, the master will issue a device
address byte consisting of 1010 (A2) (A1) (A0) (R/W) to ac-
cess the selected Turbo IC 24C128/24C256 for a read or
write operation. The A[2:0] bits must match with the address
input pins of the selected Turbo IC 24C128/24C256. If there
is a match, the selected Turbo IC 24C128/24C256 acknowl-
edges during the ninth clock cycle by pulling the SDA bus
low. If there is no match, the Turbo IC 24C128/24C256 does
not acknowledge during the ninth clock cycle and goes into
standby mode. The (R/W) bit is a high (1) for read and low (0)
for write.
DATA INPUT DURING WRITE OPERATION:
During the write operation, the Turbo IC 24C128/24C256
latches the SDA bus signal on the rising edge of the SCL
clock.
DATA OUTPUT DURING READ OPERATION:
During the read operation, the Turbo IC 24C128/24C256 se-
rially shifts the data onto the SDA bus on the falling edge of
the SCL clock.
memory address counter is automatically incremented by
one. The stop condition starts the internal EEPROM write
cycle only if the stop condition occurs in the clock cycle im-
mediately following the acknowledge (10th clock cycle). All
inputs are disabled until the completion of the write cycle. If
the WP pin is high (1), then the stop condition does not start
the internal write cycle, and the Turbo IC 24C128/24C256 is
immediately ready for the next command.
POLLING ACKNOWLEDGE:
During the internal write cycle of a write operation in the Turbo
IC 24C128/24C256, the completion of the write cycle can be
detected by polling acknowledge.The master starts acknowl-
edge polling by issuing a start condition, then followed by the
device address byte 1010 (A2) (A1) (A0) 0. If the internal
write cycle is finished, the Turbo IC 24C128/24C256 acknowl-
edges by pulling the SDA bus low. If the internal write cycle is
still ongoing, the Turbo IC 24C128/24C256 does not acknowl-
edge because it’s inputs are disabled. Therefore, the device
will not respond to any command. By using polling acknowl-
edge, the system delay for write operations can be reduced.
Otherwise, the system needs to wait for the maximum inter-
nal write cycle time, tWC, given in the spec.
MEMORY ADDRESSING:
The memory address is sent by the master in the form of 2
memory address bytes.The memory address bytes can only
be sent as part of a write operation. The most significant
address byte B(14) B(13) (B12) (B11) (B10) (B9) (B8) is sent
first, where B(14) is a “don’t care” bit in the 24C128. Then the
least significant address byte (B7) (B6) (B5) (B4) (B3) (B2)
(B1) (B0) is sent last.
POWER ON RESET:
The Turbo IC 24C128/24C256 has a Power On Reset circuit
(POR) to prevent data corruption and accidental write op-
erations during power up. On power up, the internal reset
signal is on and the Turbo IC 24C128/24C256 will not re-
spond to any command until the VCC voltage has reached
the POR threshold value.
BYTE WRITE OPERATION:
The master initiates the byte write operation by issuing a
start condition, followed by the device address byte 1010
(A2) (A1) (A0) 0, followed by 2 memory address bytes, fol-
lowed by one data byte, then a stop condition. After each
byte transfer, the Turbo IC 24C128/24C256 acknowledges
the successful data transmission by pulling the SDA bus low.
The stop condition starts the internal EEPROM write cycle,
and all inputs are disabled until the completion of the write
cycle. If the WP pin is high, then the stop condition does not
start the internal write cycle and the Turbo IC 24C128/24C256
is immediately ready for the next command.
PAGE WRITE OPERATION:
The master initiates the page write operation by issuing a
start condition, followed by the device address byte 1010
(A2) (A1) (A0) 0, followed by 2 memory address bytes, fol-
lowed by up to 64 data bytes, then a stop condition. After
each byte transfer, the Turbo IC 24C128/24C256 acknowl-
edges the successful data transmission by pulling SDA low.
After each data byte transfer, the
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