ICM108B Datasheet, PDF (4/20 Pages) List of Unclassifed Manufacturers – 1.3 million pixel Color CMOS image sensor

ICM108B 1.3 million pixel CMOS sensor
Data Sheet V 1.1 November, 2002
1. Preliminary Pin Assignment
Pin #
14
Name
CLKSEL
Class*
D, I, N
11
CLKIN
D, I, N
12
XIN
A, I
13
XOUT
A, O
33
PCLK
D, O
35
OEN
D, I, N
31
SIF ID
D, I, N
32
MSSEL
D, I, U
2
SCL
D, I/O
1
SDA
D, I/O
10
POWERDN D, I, N
17
RSET
A, I
8
RSTN
D, I, U
48
DOUT[10]
D, I/O
47
DOUT[9]
D, I/O
46
DOUT[8]
D, I/O
45
DOUT[7]
D, O
44
DOUT[6]
D, I/O
43
DOUT[5]
D, I/O
40
DOUT[4]
D, I/O
39
DOUT[3]
D, I/O
38
DOUT[2]
D, I/O
37
DOUT[1]
D, I/O
36
DOUT[0]
D, I/O
3
HSYNC
D, I/O
5
VSYNC
D, I/O
34
FLASH
D, O
15
RAMP
A, O
30,7
VDDA
P
29,9
GNDA
P
19
VDDD
P
18
GNDD
P
41,4
VDDK
P
42,6
GNDK
P
Function
Clock source selection
0: clocks pass PLL, use XIN (pin 12)
1: bypass PLL, use CLKIN (pin 11)
External clock source; bypass PLL
Crystal oscillator in, or external clock in; if external
clocks used, leave Xout (pin 13) unconnected
Crystal oscillator out
Pixel clock output
Output enable. 0: enable, 1: disable
LSB of SIF slave address
SIF master/slave selection. 0: slave, 1: master
SIF clock
SIF data
Power down control, 0: power down, 1: active
Resistor to ground = 25 KΩ @ 48 MHz main clock,
(or 50KΩ @ 24 MHz main clock)
Chip reset, active low
Data output bit 10
Data output bit 9
Data output bit 8
Data output bit 7
Data output bit 6; if pulled up/down, the initial value
of TIMING_CONTROL_LOW[2] (VSYNC polarity)
is 1/0
Data output bit 5; if pulled up/down, the initial value
of TIMING_CONTROL_LOW[1] (HSYNC polarity)
is 1/0
Data output bit 4; if pulled up/down, the initial value
of AD_IDL[3] (Sub ID) is 1/0
Data output bit 3; if pulled up/down, the initial value
of AD_IDL[2] (Sub ID) is 1/0
Data output bit 2; if pulled up/down, the initial value
of AD_IDL[1] (Sub ID) is 1/0
Data output bit 1; if pulled up/down, the initial value
of AD_IDL[0] (Sub ID) is 1/0
Data output bit 0; if pulled up/down, the synchron-
ization mode is in master/slave mode which requires
HSYNC and VSYNC operating in output/input mode
Horizontal sync signal
Vertical sync signal
Flash light control
Analog ramp output
Sensor analog power
Sensor analog ground
Sensor digital power
Sensor digital ground
Digital power
Digital ground
©2000, 2001, 2002 IC Media Corporation & IC Media Technology Corp.
11/22/2002
page 4
COMPANY CONFIDENTIAL