L64105 Datasheet, PDF (360/454 Pages) List of Unclassifed Manufacturers – AUDIO/VIDEO DECODER

Figure 10.11 DAC Output Mode: PCM Sample Precision = 20 Bit
BCLK
LRCLK
(Invert LRCLK=0)
LRCLK
(Invert LRCLK=1)
Right PCM
N-1
Right PCM
N-1
ASDATA R1 R0 S S
Left PCM
N
Left PCM
N-1
S L19 L18
(Twelve sign extension bits)
Right PCM
N
L1 L0 S S
Right PCM
N
S R19 R18
(Twelve sign extension bits)
Left PCM
N+1
Left PCM
N
R1 R0 S S
Note: S means sign-extension (0 for positive PCM values, 1 for negative PCM values).
Figure 10.12 DAC Output Mode: PCM Sample Precision = 24 Bit
BCLK
LRCLK
(Invert LRCLK=0)
LRCLK
(Invert LRCLK=1)
Right PCM
N-1
Right PCM
N-1
ASDATA R1 R0 S S
Left PCM
N
Left PCM
N-1
S L23 L22
(Eight sign extension bits)
Right PCM
N
L1 L0 S S
Right PCM
N
S R23 R22
(Eight sign extension bits)
Left PCM
N+1
Left PCM
N
R1 R0 S S
Note: S means sign-extension (0 for positive PCM values, 1 for negative PCM values).
The interface supplies four signals to the DAC:
♦ a sample clock, A_ACLK,
♦ the bit clock, BLCK,
♦ a left/right channel clock, LRCLK, and
♦ the serial audio data, ASDATA.
BCLK and A_ACLK are derived from an ACLK input in the Clock Divider
(see Section 10.10, “Clock Divider”). BCLK is at the output bit rate and
expressed as:
BCLK = Sample Freq × Sample Resolution × 2(channels)
10-28
Audio Decoder Module