L64105 Datasheet, PDF (358/454 Pages) List of Unclassifed Manufacturers – AUDIO/VIDEO DECODER

10.7 PCM FIFO Mode
The host can write four-byte, L-R PCM samples (two bytes for each
channel) into the PCM FIFO and select these values to play through the
Linear PCM Decoder. The registers associated with PCM FIFO mode are
listed in Table 10.9. The host can read the FIFO full, near full, and empty
status bits and monitor the near full signal (PREQn) for external DMA
control.
Table 10.9 PCM FIFO Mode Registers
Register Bits Name
Page Ref.
264
0
Decode Start/Stop Command
4-57
357
[7:5] Audio Decoder Mode Select [2:0] 4-81
359
[7:0] PCM FIFO Data In [7:0]
4-83
353
7
PCM FIFO Full
4-77
6
PCM FIFO Near Full
5
PCM FIFO Empty
The host uses the following sequence for PCM FIFO mode:
1. Clear the Decode Start/Stop Command bit to stop the Audio
Decoder.
2. Program the Audio Decoder Mode Selection bits to 0b111 to select
the PCM FIFO mode.
3. Using a host DMA controller, write PCM audio into the PCM FIFO
Data In register to fill the PCM FIFO. The audio data is written in the
following order; left channel LSB, left channel MSB, right channel
LSB, and right channel MSB. The PCM FIFO is 16 words deep x
16 bits wide.
4. Set the Decode Start/Stop Command bit to start the Audio Decoder.
5. Monitor the PCM FIFO status bits in Register 353 and the PREQn
output signal of the L64105. The PCM FIFO Near Full bit is cleared
when the PCM FIFO contains less than 25 unread words. When the
bit is cleared, PREQn is also asserted to the external DMA controller.
10-26
Audio Decoder Module