L64105 Datasheet, PDF (128/454 Pages) List of Unclassifed Manufacturers – AUDIO/VIDEO DECODER

Registers 207–212, and 222 and 223 (page 4-47) set the parameters for
testing the Phase-Locked Loop (PLL). The PLL test is run by setting bit
0, PLL Test, in Register 204 (page 4-43). The results from the PLL test
can be read from Register 221, (page 4-47.) Tests are run on the phase
detector and the VCO. The PLL passes the test if the frequency of the
PLL falls between the high frequency value and the low frequency value.
The PLL test interrupts the system clock and should not be attempted
when the chip is running.
Note:
Registers 207 through 212 are included for LSI Logic’s
testing purposes. Do not write to the registers without
specific directions from LSI Logic.
Figure 4.64 Registers 213–215 (0xD5–0x0D7)DMA SDRAM Target Address [18:0]
7
Reg. 213
LSB
Reg. 214
Reg. 215
MSB
3
2
0
DMA SDRAM Target Address (DMA + block) [7:0]
R/W
DMA SDRAM Target Address (DMA + block) [15:8]
R/W
Reserved
DMA SDRAM Target Address
(DMA + block) [18:16] R/W
During DMA Write and Block Move, the DMA SDRAM Target Address is
the starting address where future DMA writes will take place. This
address is automatically incremented after a 64-bit word is transferred to
SDRAM from the internal 8 x 64 write FIFO. The DMA SDRAM Target
Address should be updated by the host only when the write FIFO is
empty.
Figure 4.65 Registers 216–218 (0xD8–0x0DA) DMA SDRAM Source Address [18:0]
7
3
2
0
Reg. 216
LSB
DMA SDRAM Source Address (dma+block) [7:0]
R/W
Reg. 217
DMA SDRAM Source Address (dma+block) [15:8]
R/W
Reg. 218
MSB
Reserved
DMA SDRAM Source Address
(DMA + block) [18:16] R/W
During DMA Read and Block Move, the DMA SDRAM Source Address
is the starting address where future DMA reads will take place. This
address is automatically incremented after a 64-bit word is transferred
from SDRAM to the internal 8 x 64 read FIFO. The DMA SDRAM Source
4-46
Register Descriptions