HD49801FB Datasheet, PDF (30/43 Pages) List of Unclassifed Manufacturers – Digital Signal Processing IC for CCD Cameras

HD49801FB
• A/D input data (line delay memory R/W) transfer protocol
HD49801FB
HREFI
ADI1 to ADI9
SCKI
Start address
(state data A14 to A1)
Stop address
(state data A14 to A2)
D1
D2
D768
State data A16 DCKC: 1: Positive phase (ADI1 to ADI9 latched on the rising edge of SCKI)
0: Reverse phase (ADI1 to ADI9 latched on the falling edge of SCKI)
State data A16 HCKC: 1: Positive phase (HREFI falling edge detected on the rising edge of SCKI)
0: Reverse phase (HREFI falling edge detected on the falling edge of SCKI)
• Line delay memory R/W setting example
SCKI
HREFI
HREFI
falling edge
detection
Memory stop counter clear
Memory start address
Memory stop address
ADI1 to ADI9 (HGI = H)
ADI1 to ADI9 (HGI = L)
A14 to A1 (memory start address)
A14 to A2 (memory stop address)
A16 to A1 (mode): HCKC = 1, DCKC = 1
an bn an + 1 bn + 1
(For example, Wrn Gbn)
cn dn cn + 1 dn + 1
(For example, Grn Wbn)
an+m bn+m
cn+m dn+m
Valid data (max: 768)
The relationship between the CCD sensor complementary color signals (Wrn, Gbn, Grn, and Wrn) and
state data A7 (a, b, c, d) is determined by the relationship between the HGI input and the start address.
HGI is a line determination input, and when high, the two complementary color signals correspond to (a,
b), and when low, they correspond to (c, d).
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