HD49801FB Datasheet, PDF (3/43 Pages) List of Unclassifed Manufacturers – Digital Signal Processing IC for CCD Cameras

HD49801FB
HD49801FB
Pin Functions (cont)
Pin Pin
No. Name
Signal
I/O
35 YPO (8) Y pararell out (8): MSB O
36 YPO (7) Y pararell out (7)
O
37 YPO (6) Y pararell out (6)
O
38 CORE V_DD V_DD for core
V_DD
39 YPO (5) Y pararell out (5)
O
40 YPO (4) Y pararell out (4)
O
41 YPO (3) Y pararell out (3)
O
42 YPO (2) Y pararell out (2)
O
43 YPO (1) Y pararell out (1): LSB O
44 YPI (8) Y pararell in (8): MSB I
45 YPI (7) Y pararell in (7)
I
46 YPI (6) Y pararell in (6)
I
47 YPI (5) Y pararell in (5)
I
48 YPI (4) Y pararell in (4)
I
49 YPI (3) Y pararell in (3)
I
50 YPI (2) Y pararell in (2)
I
51 YPI (1) Y pararell in (1): LSB I
52 CPO (4) C pararell out (4): MSB O
53 CPO (3) C pararell out (3)
O
54 CPO (2) C pararell out (2)
O
55 CPO (1) C pararell out (1): LSB O
56 CPI (4) C pararell in (4): MSB I
57 CPI (3) C pararell in (3)
I
58 CPI (2) C pararell in (2)
I
59 CPI (1) C pararell in (1): LSB I
60 NRYBYO R-Y, B-Y phase out
O
61 DICKO Digital interface clock out O
62 CORE V_SS V_SS for core
V_SS
63 HREFI Horizontal reference in I
64 HGI
Horizontal gate in
I
65 SCKI
Sensor clock in
I
66 ADI (9) AD in (9): MSB
I
67 ADI (8) AD in (8)
I
68 ADI (7) AD in (7)
I
Function Description
Y digital interface output
Outputs the post-gamma compensation Y signal
V_DD
for
core,
V_DD
=
5
V
+0.25
–0.50
V
V
Y digital interface output
Y digital interface input
C digital interface output (data format: two’s
complement)
Color difference signals R-Y and B-Y
Upper to lower order
C digital interface input (data format: two’s
complement)
C digital interface phase output; high = (B-Y) phase,
low = (R-Y) phase
Digital interface clock output, frequency = fs
V_SS for core
Horizontal scan reference signal
Reference for memory start/stop, BF, CBLK, and
CSYNC
Line signals (two types) determination input; high = a,
b; low = c, d (state data A7)
Sensor clock (system clock) fs input
A/D input
3