A54SX16 Datasheet, PDF (30/57 Pages) List of Unclassifed Manufacturers – 54SX Family FPGAs

54SX Family FPGAs
A54SX16P Timing Characteristics (continued)
(Worst-Case Commercial Conditions, V_CCR= 4.75V, V_CCA,V_CCI = 3.0V, T_J = 70°C)
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max.
Dedicated (Hard-Wired) Array Clock Network
t_HCKH
Input LOW to HIGH
(Pad to R-Cell Input)
t_HCKL
Input HIGH to LOW
(Pad to R-Cell Input)
t_HPWH
t_HPWL
t_HCKSW
t_HP
f_HMAX
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Maximum Skew
Minimum Period
Maximum Frequency
Routed Array Clock Networks
1.2
1.4
1.5
1.8
1.2
1.4
1.6
1.9
1.4
1.6
1.8
2.1
1.4
1.6
1.8
2.1
0.2
0.2
0.3
0.3
2.7
3.1
3.6
4.2
350
320
280
240
t_RCKH
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
t_RCKL
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
t_RCKH
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
t_RCKL
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
t_RCKH
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
t_RCKL
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
t_RPWH
t_RPWL
t_RCKSW
t_RCKSW
t_RCKSW
Min. Pulse Width HIGH
Min. Pulse Width LOW
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
TTL Output Module Timing
1.6
1.8
2.1
2.5
1.8
2.0
2.3
2.7
1.8
2.1
2.5
2.8
2.0
2.2
2.5
3.0
1.8
2.1
2.4
2.8
2.0
2.2
2.5
3.0
2.1
2.4
2.7
3.2
2.1
2.4
2.7
3.2
0.5
0.5
0.5
0.7
0.5
0.6
0.7
0.8
0.5
0.6
0.7
0.8
t_DLH
Data-to-Pad LOW to HIGH
t_DHL
Data-to-Pad HIGH to LOW
t_ENZL
Enable-to-Pad, Z to L
t_ENZH
Enable-to-Pad, Z to H
t_ENLZ
Enable-to-Pad, L to Z
t_ENHZ
Enable-to-Pad, H to Z
TTL/PCI Output Module Timing
2.4
2.8
3.1
3.7
2.3
2.9
3.2
3.8
3.0
3.4
3.9
4.6
3.3
3.8
4.3
5.0
2.3
2.7
3.0
3.5
2.8
3.2
3.7
4.3
t_DLH
t_DHL
t_ENZL
t_ENZH
t_ENLZ
t_ENHZ
Data-to-Pad LOW to HIGH
Data-to-Pad HIGH to LOW
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
1.5
1.7
2.0
2.3
1.9
2.2
2.4
2.9
2.3
2.6
3.0
3.5
1.5
1.7
1.9
2.3
2.7
3.1
3.5
4.1
2.9
3.3
3.7
4.4
Units
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
v3.1