A54SX16 Datasheet, PDF (23/57 Pages) List of Unclassifed Manufacturers – 54SX Family FPGAs

54SX Family FPGAs
Output Buffer Delays
E
D
TRIBUFF
PAD To AC test loads (shown below)
In
Out
V_OL
V_CC
50% 50%
V_OH
1.5V
GND
1.5V
t_DLH
t_DHL
V_CC
En _{50% 50%}
V_CC
Out
1.5V
V_OL
GND
10%
t_ENZL
t_ENLZ
AC Test Loads
Load 1
(Used to measure
propagation delay)
To the output
under test
Load 2
(Used to measure enable delays)
V_CC
GND
35 pF
To the output
under test
R to V_CC for t_PZL
R to GND for t_PZH
R = 1 kΩ
35 pF
En
Out
GND
V_CC
50% 50%
V_OH
1.5V
GND
90%
t_ENZH
t_ENHZ
Load 3
(Used to measure disable delays)
V_CC
GND
To the output
under test
R to V_CC for t_PLZ
R to GND for t_PHZ
R = 1 kΩ
5 pF
Input Buffer Delays
PAD
INBUF
Y
In
Out
GND
3V
1.5V 1.5V
V_CC
50%
0V
50%
t_INY
t_INY
C-Cell Delays
S
AY
B
S, A or B
Out
GND
Out
V_CC
50% 50%
V_CC
50%
GND
50%
t_PD
50%
t_PD
t_PD
GND
t_PD
V_CC
50%
v3.1
23