GVT71128D32 Datasheet, PDF (3/13 Pages) List of Unclassifed Manufacturers – 128K X 32 SYNCHRONOUS BURST SRAM

GALVANTECH,
GVT71128D32
128K X 32 SYNCHRONOUS BURST SRAM
PIN ASSIGNMENT (Top View)
NC
DQ17
DQ18
VCCQ
VSSQ
DQ19
DQ20
DQ21
DQ22
VSSQ
VCCQ
DQ23
DQ24
NC
VCC
NC
VSS
DQ25
DQ26
VCCQ
VSSQ
DQ27
DQ28
DQ29
DQ30
VSSQ
VCCQ
DQ31
DQ32
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
100-pin PQFP
15
66
16
or
65
17
100-pin TQFP
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQ16
DQ15
VCCQ
VSSQ
DQ14
DQ13
DQ12
DQ11
VSSQ
VCCQ
DQ10
DQ9
VSS
NC
VCC
ZZ
DQ8
DQ7
VCCQ
VSSQ
DQ6
DQ5
DQ4
DQ3
VSSQ
VCCQ
DQ2
DQ1
NC
PIN DESCRIPTIONS
QFP PINS
37, 36, 35, 34, 33,
32, 100, 99, 82, 81,
44, 45, 46, 47, 48,
49, 50
93,94,95,96
87
SYMBOL
A0-A16
BW1#,
BW2#,
BW3#,
BW4#
BWE#
88
GW#
89
CLK
98
CE#
92
CE2#
TYPE
Input-
Synchronous
DESCRIPTION
Addresses: These inputs are registered and must meet the setup and hold times around
the rising edge of CLK. The burst counter generates internal addresses associated with A0
and A1, during burst cycle and wait cycle.
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ cycle. BW1#
controls DQ1-DQ8. BW2# controls DQ9-DQ16. BW3# controls DQ17-DQ24. BW4#
controls DQ25-DQ32. Data I/O are high impedance if either of these inputs are LOW,
conditioned by BWE# being LOW.
Write Enable: This active LOW input gates byte write operations and must meet the setup
and hold times around the rising edge of CLK.
Global Write: This active LOW input allows a full 32-bit WRITE to occur independent of the
BWE# and BWn# lines and must meet the setup and hold times around the rising edge of
CLK.
Clock: This signal registers the addresses, data, chip enables, write control and burst
control inputs on its rising edge. All synchronous inputs must meet setup and hold times
around the clock’s rising edge.
Chip Enable: This active LOW input is used to enable the device and to gate ADSP#.
Chip Enable: This active LOW input is used to enable the device.
November 20, 1999
Rev. 11/9 9
3
Galvantech, Inc. reserves the right to change products or specifications without notice.