GVT71128D32 Datasheet, PDF (1/13 Pages) List of Unclassifed Manufacturers – 128K X 32 SYNCHRONOUS BURST SRAM

GALVANTECH,
GVT71128D32
128K X 32 SYNCHRONOUS BURST SRAM
SYNCHRONOUS
BURST SRAM
PIPELINED OUTPUT
128K x 32 SRAM
+3.3V SUPPLY, PIPELINED, SINGLE
CYCLE DESELECT, BURST COUNTER
FEATURES
• Fast access times: 4.8, 5, 6, and 7ns
• Fast clock speed: 100, 83, and 66MHz
• Provide high performance 3-1-1-1 access rate
• Fast OE# access times: 5, 6, and 7ns
• Optimal for depth expansion (one cycle chip deselect to
eliminate bus contention)
• Single +3.3V -5% and +10%power supply
• Support +2.5V I/O
• 5V tolerant inputs except I/O’s
• Clamp diodes to VSSQ at all outputs
• Common data inputs and data outputs
• BYTE WRITE ENABLE and GLOBAL WRITE control
• Three chip enables for depth expansion and address
pipelin e
• Address, control, input, and output pipeline registers
• Internally self-timed WRITE CYCLE
• Burst control pins (interleaved or linear burst sequence)
• Automatic power-down for portable applications
• High density, high speed packages
• Low capacitive bus loading
• High 30pF output drive capability at rated access time
OPTION S
• Timing
4.8ns access/10ns cycle
5ns access/10ns cycle
6ns access/12ns cycle
7ns access/15ns cycle
MARKING
-4
-5
-6
-7
• Packages
100-pin TQFP
T
• Temperature
Commercial
Industrial
None (0°C to 70°C)
I
(-40°C to 85°C)
GENERAL DESCRIPTION
The Galvantech Synchronous Burst SRAM family
employs high-speed, low power CMOS designs using
advanced triple-layer polysilicon, double-layer metal
technology. Each memory cell consists of four transistors and
two high valued resistors.
The GVT71128D32 SRAM integrates 131,072x32
SRAM cells with advanced synchronous peripheral circuitry
and a 2-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
chip enable (CE#), depth-expansion chip enables (CE2# and
CE2), burst control inputs (ADSC#, ADSP#, and ADV#),
write enables (BW1#, BW2#, BW3#, BW4#,and BWE#), and
global write (GW#).
Asynchronous inputs include the output enable (OE#)
and burst mode control (MODE). The data outputs (Q),
enabled by OE#, are also asynchronous.
Addresses and chip enables are registered with either
address status processor (ADSP#) or address status controller
(ADSC#) input pins. Subsequent burst addresses can be
internally generated as controlled by the burst advance pin
(ADV#).
Address, data inputs, and write controls are registered on-
chip to initiate self-timed WRITE cycle. WRITE cycles can
be one to four bytes wide as controlled by the write control
inputs. Individual byte write allows individual byte to be
written. BW1# controls DQ1-DQ8. BW2# controls DQ9-
DQ16. BW3# controls DQ17-DQ24. BW4# controls DQ25-
DQ32. BW1#, BW2# BW3#, and BW4# can be active only
with BWE# being LOW. GW# being LOW causes all bytes to
be written. This device also incorporates pipelined enable
circuit for easy depth expansion without penalizing system
performance.
The GVT71128D32 operates from a +3.3V power
supply. All inputs and outputs are TTL-compatible. The
device is ideally suited for 486, Pentium^TM, 680x0, and
PowerPC^TM systems and for systems that are benefited from a
wide synchronous data bus.
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051
Tel [phone] Fax [phone] Web Site www.galvantech.com
Rev. 11/9 9
Pentium is a trademark of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
Galvantech, Inc. reserves the right to change
products or specifications without notice.