P-51 Datasheet, PDF (2/4 Pages) List of Unclassifed Manufacturers – Peripheral 8051 System on a Chip

P-51
Think of the P-51 as the ultimate peripheral. You’ve used
programmable timers, counters, interrupt controllers, and other
special purpose peripherals. Now the P-51 allows you to directly
connect a general purpose 8051 computer, with all its hardware and
software resources, to almost any bus: ISA, PC/104, or micro-controller. You
can drive a P-51 directly from an 8051, 386EX, or Z80. Via the P-51 chip select
pin you can even hang multiple P-51s on a single bus.
P-51 Peripheral to an x86
Base
PgAddr
x86
Host
Processor
ADDR (20)
DATA (8)
IRQ
3.3v
ALE
P0
P1
P2
P3
In the case of the 20-bit address
presented by the EISA bus, the
high order bits are compared to the
Base Page address pins, and the
P-51 is enabled when addresses
match, thereby allowing the P-51 to
be located at a specific range in
x86 address space. By writing to a
P-51 control register, the x86 can
select (and enable) an IRQ signal
(from IRQ3 to IRQ15).
P-51 Peripheral to an 8051
8051
Host ^P2
uC _ALE
P0
RESET
ADDR
ADD/DATA
INTERRUPT
In this example a standard 8051
uses P0, P2, and control strobes to
control a P-51, effectively doubling
P0
8051 resources. The internal dual
port RAM serves as a mailbox for
P1
communicating between the two
P2
and also can be used as 4K RAM
data for a standard 8051. The
P3
standard 8051 can download code
to the P51 while holding it in reset,
then release the P51 to run the
code. Think of the possibilities!
Breakpoint and Single Stepping
The P-51 supports breakpoints and single
stepping. When the P-51 encounters a
breakpoint in the code, the P-51 copies its
program counter into dual port RAM,
interrupts the host with a breakpoint interrupt,
and then waits for the host. The host
performs any action that is appropriate, then
releases the P-51 by clearing a “wait” bit in a
dual port RAM-mapped control register. The
host can set a single-step bit in the control
register, which causes the P-51 to interrupt
the host after every instruction execution.
The combination of break and step provides
features that would require an in-circuit
emulator in a standard 8051
20APR2000
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