SA25F020 Datasheet, PDF (16/37 Pages) List of Unclassifed Manufacturers – 2Mb Serial Flash with 25MHz SPI Bus Interface

Write Protect
The WPb pin enables write operations to
the status register when held high. When
the WPb pin is brought low and the
WPBEN bit is 1, all write operations to the
status register are inhibited (for more
details, refer to Table 10, page 21). If WPb
goes low while CSb is still low, the write to
the status register is interrupted. If the
internal write cycle has already been
initiated, WPb going low has no effect on
any write operations to the status register.
The WPb pin function is blocked when the
WPBEN bit in the status register is 0,
which enables the user to install the
SA25F020 in a system with the WPb pin
tied to ground but still able to write to the
status register. All WPb pin functions are
enabled when the WPBEN bit is set to 1.
SA25F020 Advanced Information
SAIFUN
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