SA25F020 Datasheet, PDF (13/37 Pages) List of Unclassifed Manufacturers – 2Mb Serial Flash with 25MHz SPI Bus Interface

Signal Description
Chip Select (CSb)
This is an active-low input pin to the device
that is generated by the master controlling
the device. A low level on this pin selects
the device, while a high level deselects the
device. All serial communications with the
device are enabled only when this pin is
held low.
Serial Clock (SCK)
This is an input pin to the device that is
generated by the master controlling the
device. It is a clock signal that
synchronizes the communication between
a master and the device. All input
information (SI) to the device is latched on
the rising edge of this clock input, while
output data (SO) from the device is driven
after the falling edge of this clock input.
Serial Input (SI)
This is an input pin to the device that is
generated by the master controlling the
device. The master transfers input
information (instruction, addresses and the
data to be programmed) into the device
serially via this pin. This input information is
latched on the rising edge of the SCK.
SA25F020 Advanced Information
SAIFUN
13
Serial Output (SO)
This is an output pin from the device that is
used to transfer output data to the
controlling master. Output data is serially
shifted out on this pin after the falling edge
of the SCK.
Hold (HOLDb)
This is an active low input pin to the device
that is generated by the master controlling
the device. When driven low, this pin
suspends any current communication with
the device. The suspended communication
can be resumed by driving this pin high.
This feature eliminates the need to
re-transmit the entire sequence by
enabling the master to resume the
communication from where it was left off.
This pin should be tied high if this feature is
not used. Refer to Hold Condition,
page 15, for additional details.
Write Protect (WPb)
This is an active low input pin to the device.
This pin allows enabling and disabling of
writes to the device's memory array and
status register. When this pin is held low,
writes to the memory array and status
register are disabled; when it is held high,
they are enabled. Refer to Write Protect,
page 16, for additional details.