SED1351 Datasheet, PDF (13/18 Pages) List of Unclassifed Manufacturers – GRAPHICS LCD CONTROLLER

SED1351
5. LCD Connector Terminals
Pin Name
UD0 to UD3
LD0/UD4 to
LD3/UD7
XSCL
LP
WF
YD
LCDENB
Type
F0A
Pin No.
FLB
Pin No.
Drv
Description
I/O 91 to 94 89 to 92
O 95 to 98 93 to 96
LCD display data. UD0 to UD3 are the upper panel
display data in the signal panel or double panel
drive panel mode. LD0/UD4 to LD3/UD7 are the lower
panel display data in the double panel drive mode.
UD0 to UD3, and LD0/UD4 to LD3/UD7 are used for 8-
bit data transfer in the single panel drive mode.
O
87
85
This single is a shift clock for display data transfer.
Take the UD0 to UD3, LD0/UD4 to LD3/UD7 display
data into LCDs by the falling edge of XSCL.
O
88
86
This pin provides both a display data latch pulse and
a scan signal transfer clock. Upon completion of trans-
ferring the LCD data on one line, display data can be
latched or a scan signal transferred by the falling edge
of LP.
O
89
87
This pin provides a frame signal used for LCD AC
driving.
O
90
88
This pin provides a scanning line start pulse. The
signal is “H” active. Allow the scanning line drive IC to
take in YD by the falling edge of LP.
The SED1351 has two lines of retracing; if two scan-
ning line drive ICs are cascade-connected for the
upper and lower panels in the double panel drive
mode, two lines must be provided between the upper
and lower scanning line drive outputs.
O
86
84
This pin provides the data which is set in bit 1 (D1) of
the mode register (R1). LCDENB goes “L” when the
system is reset; it can be effectively used for LCD
power control.
209