SED1351 Datasheet, PDF (12/18 Pages) List of Unclassifed Manufacturers – GRAPHICS LCD CONTROLLER

SED1351
Combinations of Control Pins
IOCS
1
0
0
1
1
IOWR
*
0
1
1
1
IORD
*
1
0
1
1
MEMCS
1
1
1
0
0
MEMWR
*
1
1
0
1
MEMRD
*
1
1
1
0
Note: Any combination other than those listed above will cause a system error.
1 = “H” (high)
0 = “L” (low)
* = Don’t care
Operation
Invalid
Write to control register
Read from control register
Write to VRAM
Read from VRAM
2. VRAM Connector Terminals
Pin Name
Type
F0A
Pin No.
FLB
Pin No.
Drv
Description
VD0 to VD15
I/O 68 to 78, 68 to 83
81 to 85
These pins are interfaced with the VRAM data bus.
For a 16-bit MPU configuration, VD0 to VD7 must be
connected to even addresses, and VD8 to VD15 to
odd addresses. For an 8-bit configuration, VD8 to
VD15 must be connected to VDD.
VA0 to VA12
O 47 to 59 45 to 49,
52 to 59
These pins are interfaced with the VRAM address
bus and chip select pins.
VA13/VCS7 to O
VA15/VCS5
VCS0 to VCS4 O
60 to 62 60 to 62
67 to 63 67 to 63
The SED1351 has chip select pins that can directly
control eight 64K SRAMs (8K bytes each) or two
256K SRAMs (32K bytes) in the 64K VRAM space.
See Technical Manual for details.
VWE
O
46
44
This signal is used for writing data to the VRAM. It is “L”
active, and must be connected to the WE pin of the
VRAM.
3. Oscillator Terminals
Pin Name
OSC1
OSC2
Type
I
O
F0A
Pin No.
99
100
FLB
Pin No.
97
98
Drv
Description
The OSC1 (input) and OSC2 (output) pins gener-
ate clocks for internal operation. They allow crystal
oscillation and external clock input.
4. Power Terminals
Pin Name
VDD
VSS
Type
—
—
F0A
Pin No.
2, 79
1, 80
FLB
Pin No.
51, 100
50, 99
Drv
Description
The power supply pins include two VDDs and two
VSSs. Apply +5V or +3V to VDD and 0V to VSS. A
capacitor (4.7 µF or more) must be connected near
each pair of VDD/VSS pins.
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