SED1351 Datasheet, PDF (11/18 Pages) List of Unclassifed Manufacturers – GRAPHICS LCD CONTROLLER

SED1351
s PIN DESCRIPTION
1. System Connector Terminals (at MPU)
Pin Name
DB0 to DB15
AB0 to AB15
BHE
IOCS
IOWR
IORD
MEMCS
MEMWR
MEMRD
READY
MPUCLK
MPUSEL
RESET
Type
I/O
I
I
I
I
I
I
I
I
O
I
I
I
F0A
Pin No.
30 to 45
14 to 29
13
3
4
5
6
7
8
9
10
12
11
FLB
Pin No.
28 to 43
12 to 27
11
1
2
3
4
5
6
7
8
10
9
Drv
Description
These pins are interfaced with the MPU data bus.
When using an 8-bit MPU, connect DB8 to DB15 to
VDD.
These pins are interfaced with the MPU address bus.
If multiplexed address signals are used, connect them
via latch circuits. A control register is selected by AB0
to AB3. Correspondence of the MPU address bus to
the VRAM address bus is such that ABi = VAi (where
i is a pin number).
This signal is a bus high enable signal where a 16-bit
MPU is used. It goes “L” (low) when an odd address is
encountered. When using an 8-bit MPU configuration,
connect the BHE pin to VDD.
This pin selects a control register contained in the
SED1351. It is “L” active, and must be assigned to
MPU I/O space.
This signal is used for writing data into a control
register contained in the SED1351. It is “L” active, and
must go “L” when it encounters an OUT instruction
from the MPU.
This signal is used for reading data from a control
register contained in the SED1351. It is “L” active, and
must go “L” when it encounters an IN instruction from
the MPU.
This signal is used for selecting VRAM. It is “L” active,
and must be assigned to MPU memory space.
This signal is used for writing data to the VRAM. It is “L”
active, and must go “L” when it encounters a memory
write instruction from the MPU.
This signal is used for reading data from the VRAM. It
is “L” active, and must go “L” when it encounters a
memory read instruction from the MPU.
This signal requests the MPU to wait. It goes “L” by the
falling edge of IOCS or MEMCS. It goes “H” by the
rising edge of MPUCLK after completion of the
SED1351 internal processing. Since READY is not a
tri-state pin, it needed not be pulled up and must be
connected directly to the READY (WAIT) terminal of
the MPU.
This pin accepts an MPU clock. The MPU wait state is
cleared by the rising edge of MPUCLK.
This signal is connected to either VDD or VSS for
selection of an MPU.
MPUSEL = VSS 8-bit MPU (e.g., Z80, V20, i8088)
MPUSEL = VDD 16-bit MPU (e.g., V30, i8086)
The MPU reset signal comes to this pin. It is “H” active,
and initializes a control register.
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