W65C02S Datasheet, PDF (9/40 Pages) List of Unclassifed Manufacturers – Microprocessor

The Western Design Center, Inc.
W65C02S Data Sheet
3 PIN FUNCTION DESCRIPTION
3.1 Address Bus (A0-A15)
The sixteen bit Address Bus formed by A0-A15, address memory and I/O registers that exchange data on the Data
Bus. The address lines can be set to the high impedance state by the Bus Enable (BE) signal.
3.2 Bus Enable (BE)
The Bus Enable (BE) input signal provides external control of the Address, Data and the RWB buffers. When Bus
Enable is high, the Address, Data and RWB buffers are active. When BE is low, these buffers are set to the high
impedance status. Bus Enable is an asynchronous signal.
3.3 Data Bus (D0-D7)
The eight Data Bus lines D0-D7 are used to provide instructions, data and addresses to the microprocessor and
exchange data with memory and I/O registers. These lines may be set to the high impedance state by the Bus Enable
(BE) signal.
3.4 Interrupt Request (IRQB)
The Interrupt Request (IRQB) input signal is used to request that an interrupt sequence be initiated. The program
counter (PC) and Processor Status Register (P) are pushed onto the stack and the IRQB disable (I) flag is set to a “1”
disabling further interrupts before jumping to the interrupt handler. These values are used to return the processor to
its original state prior to the IRQB interrupt. The IRQB low level should be held until the interrupt handler clears
the interrupt request source. When Return from Interrupt (RTI) is executed the (I) flag is restored and a new
interrupt can be handled. If the (I) flag is cleared in an interrupt handler, nested interrupts can occur. The Wait-for-
Interrupt (WAI) instruction may be used to reduce power and synchronize with, as an example timer interrupt
requests.
3.5 Memory Lock (MLB)
The Memory Lock (MLB) output may be used to ensure the integrity of Read-Modify-Write instructions in a
multiprocessor system. Memory Lock indicates the need to defer arbitration of the bus cycle when MLB is low.
Memory Lock is low during the last three cycles of ASL, DEC, INC, LSR, ROL, ROR, TRB, and TSB memory
referencing instructions.
3.6 Non-Maskable Interrupt (NMIB)
A negative transition on the Non-Maskable Interrupt (NMIB) input initiates an interrupt sequence after the current
instruction is completed. Since NMIB is an edge-sensitive input, an interrupt will occur if there is a negative
transition while servicing a previous interrupt. Also, after the edge interrupt occurs no further interrupts will occur if
NMIB remains low. The NMIB signal going low causes the Program Counter (PC) and Processor Status Register
information to be pushed onto the stack before jumping to the interrupt handler. These values are used to return the
processor to it's original state prior to the NMIB interrupt.
The Western Design Center, Inc.
W65C02S Data Sheet
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