W65C02S Datasheet, PDF (38/40 Pages) List of Unclassifed Manufacturers – Microprocessor

The Western Design Center, Inc.
8.1 Features:
W65C02S Datasheet
W65C02S 8-bit MPU, total access to all control lines, Memory Bus, Programmable I/O Bus, PC Interface, 20 I/O lines, easy
oscillator change, 32K SRAM, 32K EPROM, W65C22S Versatile Interface Adapter VIA peripheral chip, on-board matrix,
CPLD for Memory map decoding, hardware breakpoints and ASIC design.
The CPLD chip is a XILINX XC95108 for changing the chip select and I/O functions if required. To change the CPLD chip
to suit your own setup, you need XILINX Data Manager for the XC95108 CPLD chip. The W65C02DB includes an on-
board programming header for JTAG configuration. For more details refer to the circuit diagram. The on-board W65C02S
and the W65C22S devices have measurement points for core power consumption. Power input is provided by an optional
power board which plugs into the 10 pin power header.
An EPROM programmer or an EPROM emulator is required to reprogram the EPROM. WDC’s (W65SDS) Software
Development System includes a W65C02S Assembler and Linker, W65C02S C-Compiler and Optimizer, and W65C02S
Simulator/Debugger. WDC’s PC IO daughter board can be used to connect the Developer Board to the parallel port of a PC
for In-Circuit Debugging.
8.2 Memory map:
CS1B:
CS3B:
CS2B:
8000-FFFF
⇒
0000-00EF & 0100-7FFF ⇒
00F0-00FF
⇒
EPROM (27C256)
SRAM (62C256)
VIA(W65C22S)
8.3 Cross-Debugging Monitor Program
The Cross-Debugging Monitor Programs of the Developer Boards are located in the directory
<drive>:\WDC_SDS\DEBUG\WDCMON\
This directory contains the source and the batch files for all of the monitor programs. These programs can be burned into an
EPROM and used with the WDC evaluation boards (Developer Boards) and the WDC IO (or ZIO-1) daughter board to
interface to the parallel port of a PC. Then, the WDCDB.EXE debugger can be used to download programs, single step, set
breakpoints, examine memory, etc for In-Circuit Debugging (ICD).
The monitors have been designed to run correctly with a W65C02 MPU (WDCMON_1), W65C816 MPU (WDCMON_2),
W65C134 MCU (WDC134), or W65C265 MCU (WDC265). It detects the appropriate CPU type on RESET and operates
accordingly.
8.4 BUILDING
The batch files assemble the program and link it producing Motorola S-Record output. This can be changed by using a
different option with the WDCLN linker
The Western Design Center, Inc.
W65C02S Datasheet
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