SII161A Datasheet, PDF (9/22 Pages) List of Unclassifed Manufacturers – SiI 161A PanelLink Receiver

Silicon Image, Inc.
SiI 161A
SiI-DS-0009-D
Output Pins Description
Pin
Name
Pin # Type
QE23- See SiI Out
QE0
161A
Pin
Diagram
QO23- See SiI Out
QO0 _161A
Pin
Diagram
ODCK
44
Out
DE
46
Out
HSYNC 48
Out
VSYNC 47
Out
CTL1
40
Out
CTL2
41
Out
CTL3
42
Out
Description
Output Even Data[23:0] corresponds to 24-bit pixel data for 1-pixel/clock input mode
and to the first 24-bit pixel data for 2-pixels/clock mode.
Output data is synchronized with output data clock (ODCK).
Refer to the TFT Signal Mapping application note (SiI/AN-0007) which tabulates the
relationship between the input data to the transmitter and output data from the
receiver.
A low level on PD or PDO will put the output drivers into a high impedance (tri-state)
mode. A weak internal pull-down device brings each output to ground.
Output Odd Data[23:0] corresponds to the second 24-bit pixel data for 2-pixels/clock
mode.
During 1-pixel/clock mode, these outputs are driven low.
Output data is synchronized with output data clock (ODCK).
Refer to the TFT Signal Mapping application note (SiI/AN-0007) which tabulates the
relationship between the input data to the transmitter and output data from the
receiver.
A low level on PD or PDO will put the output drivers into a high impedance (tri-state)
mode. A weak internal pull-down device brings each output to ground.
Output Data Clock. This output can be inverted using the OCK_INV pin. A low level on
PD or PDO will put the output driver into a high impedance (tri-state) mode. A weak
internal pull-down device brings the output to ground.
Output Data Enable. This signal qualifies the active data area. A HIGH level signifies
active display time and a LOW level signifies blanking time. This output signal is
synchronized with the output data. A low level on PD or PDO will put the output driver
into a high impedance (tri-state) mode. A weak internal pull-down device brings the
output to ground. In Dual Link Applications, the DE output pin of the Master is
connected to the SYNC input pin of the Slave.
Horizontal Sync input control signal.
Vertical Sync input control signal.
General output control signal 1. This output is not powered down by PDO.
General output control signal 2.
General output control signal 3.
A low level on PD or PDO will put the output drivers (except CTL1 by PDO) into a high
impedance (tri-state) mode. A weak internal pull-down device brings each output to
ground.
Silicon Image, Inc.
9
Subject to Change without Notice