SII161A Datasheet, PDF (1/22 Pages) List of Unclassifed Manufacturers – SiI 161A PanelLink Receiver

SiI 161A PanelLink^® Receiver
Datasheet
March 2001
General Description
The SiI 161A receiver uses PanelLink Digital technology to support high
resolution displays up to UXGA. The SiI 161A receiver supports up to true
color panels (24 bit/pixel, 16.7M colors) in 1 or 2 pixels/clock mode. In
addition, the receiver data output is time staggered to reduce ground bounce
that affects EMI. Since all PanelLink products are designed on scaleable
CMOS architecture to support future performance requirements while
maintaining the same logical interface, system designers can be assured that
the interface will be fixed through a number of technology and performance
generations.
PanelLink Digital technology simplifies PC and display interface design
by resolving many of the system level issues associated with high-speed
mixed signal design, providing the system designer with a digital interface
solution that is quicker to market and lower in cost.
Features
• Low Power: 3.3V core operation
• Time staggered data output for reduced ground
bounce
• Sync Detect: for Plug & Display “Hot Plugging”
• Cable Distance Support: over 5m with twisted-pair,
fiber-optics ready
• Compliant with DVI 1.0 (DVI is backwards
compatible with VESA^® P&D^TM and DFP)
§ Supports Dual-Link operation up to 330 Mega-
pixels/second
SiI 161A Pin Diagram
CONTROLS
GPO
EVEN 8-bits RED
QO2 51
QO3 52
QO4 53
QO5 54
QO6 55
QO7 56
OVCC 57
OGND 58
QO8 59
QO9 60
QO10 61
QO11 62
QO12 63
QO13 64
QO14 65
QO15 66
VCC 67
GND 68
QO16 69
QO17 70
QO18 71
QO19 72
QO20 73
QO21 74
QO22 75
Silicon Image, Inc.
SiI 161A
100-Pin TQFP
(Top View)
DIFFERENTIALSIGNAL
25 QE13
24 QE12
23 QE11
22 QE10
21 QE9
20 QE8
19 OGND
18 OVCC
17 QE7
16 QE6
15 QE5
14 QE4
13 QE3
12 QE2
11 QE1
10 QE0
9 PDO
8 SCDT
7 STAG_OUT/SYNC
6 VCC
5 GND
4 PIXS/M_S
3 ST
2 PD
1 S_D
PLL
Subject to Change without Notice