SII161A Datasheet, PDF (15/22 Pages) List of Unclassifed Manufacturers – SiI 161A PanelLink Receiver

Silicon Image, Inc.
SiI 161A
SiI-DS-0009-D
The Master receiver is configured by tieing the M_S pin to HIGH. When it is in Dual Link mode, the Master
receiver is in one-pixel per clock mode outputting the EVEN data for the panel. The Master receiver’s ODD data
bus is tri-stated to allow the Slave receiver’s EVEN data bus to be used as the ODD data bus for the panel.
When it is in Single Link mode, the Master receiver is in two-pixels per clock mode outputting both the EVEN
and ODD data for the panel. The Slave receiver’s EVEN data bus is tri-stated to allow the Master receiver’s ODD
data bus to be used as the ODD data for the panel.
The DE output pin of the Master receiver is connected to the SYNC input pin of the Slave receiver. This is used
for output synchronization between the Master receiver and Slave receiver. DE, HSYNC, VSYNC, and ODCK for
the panel are all taken from the Master receiver.
Slave –
The Slave receiver is always configured for Dual Link (one pixel/clock) operation. This is accomplished by tieing
the S_D pin to HIGH. The Slave receiver is never used in Single Link mode since the Master receiver is the
primary receiver for Single Link Operation.
The Slave receiver is configured by tieing the M_S pin to LOW. The Slave receiver will always contain the ODD
data bus for the panel in Dual Link operation. Therefore, it will never be in two-pixels per clock mode.
The SCDT output pin of the Slave receiver is connected to the S_D input pin of the Master receiver to
automatically configure the Master for either Single or Dual Link mode depending upon whether the Slave
receiver is active or not.
The SYNC input pin of the Slave receiver is connected to the DE output pin of the Master receiver for
synchronization.
Since DE, HSYNC, VSYNC, and ODCK for the panel are all taken from the Master receiver, these pins are not
connected from the Slave receiver.
Power Down Outputs –
The Slave receiver’s outputs are automatically tri-stated in Single Link mode, since it is not active. The Master
receiver’s outputs are automatically tri-stated in Single or Dual Link mode when there are no sync signals
coming from the transmitter. Both the Master and Slave receiver’s outputs can also be tri-stated by driving the
PDO pins to LOW manually.
For additional information about dual link operation, please see Application Notes SiI-AN-0030, (SiI161A Dual
Link Receiver Implementation) and SiI-AN-0037 (SiI168 Transmitter Dual Link Applications).
Silicon Image, Inc.
15
Subject to Change without Notice