MEM4X16E43VTW-5 Datasheet, PDF (9/24 Pages) List of Unclassifed Manufacturers – 4 MEG x 16 EDO DRAM

CAPACITANCE
(Note: 2)
PARAMETER
Input Capacitance: Address pins
Input Capacitance: RAS#, CAS#, WE#, OE#
Input/Output Capacitance: DQ
4 MEG x 16
EDO DRAM
SYMBOL
CI1
CI2
CIO
MAX
5
7
7
UNITS
pF
pF
pF
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +3.3V ±0.3V)
AC CHARACTERISTICS
PARAMETER
Access time from column address
Column-address setup to CAS# precharge
Column-address hold time (referenced to RAS#)
Column-address setup time
Row-address setup time
Column address to WE# delay time
Access time from CAS#
Column-address hold time
CAS# pulse width
CAS# LOW to “Don?t Care” during Self Refresh
CAS# hold time (CBR Refresh)
Last CAS# going LOW to first CAS# to return HIGH
CAS# to output in Low-Z
Data output hold after CAS# LOW
CAS# precharge time
Access time from CAS# precharge
CAS# to RAS# precharge time
CAS# hold time
CAS# setup time (CBR Refresh)
CAS# to WE# delay time
WRITE command to CAS# lead time
Data-in hold time
Data-in setup time
Output disable
Output enable time
OE# hold time from WE# during
READ-MODIFY-WRITE cycle
OE# HIGH hold time from CAS# HIGH
OE# HIGH pulse width
OE# LOW to CAS# HIGH setup time
Output buffer turn-off delay
OE# setup prior to RAS# during HIDDEN REFRESH cycle
SYMBOL
t_AA
t_ACH
t_AR
t_ASC
t_ASR
t_AWD
t_CAC
t_CAH
t_CAS
t_CHD
t_CHR
t_CLCH
t_CLZ
t_COH
t_CP
t_CPA
t_CRP
t_CSH
t_CSR
t_CWD
t_CWL
t_DH
t_DS
t_OD
t_OE
t_OEH
t_OEHC
t_OEP
t_OES
t_OFF
t_ORD
MIN
12
38
0
0
42
8
8
15
8
5
0
3
8
5
38
5
28
8
8
0
0
8
-5
MAX
25
13
10,000
28
12
12
5
5
4
0
12
0
MIN
15
45
0
0
49
10
10
15
10
5
0
3
10
5
45
5
35
10
10
0
0
10
-6
MAX
30
15
10,000
35
15
15
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
28
28
18
29
28
30, 32
4, 31
31
29
13, 33
29
31
31
4, 28
18, 28
31
19, 29
19, 29
24, 25
20
25
10
ns
5
ns
5
ns
0
15
ns 17, 24, 29
0
ns
9