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GP520A Datasheet, PDF (9/10 Pages) List of Unclassifed Manufacturers – Programmable Analog Signal Processor
OUTPUT STAGE
PARAMETER
Quiescent Voltage on Pad 17
Min Receiver Bias Voltage
Max Receiver Bias Voltage
Input Resistance Pad 17
Internal Feedback Resistor
Max Sinking Current (Pad 11)
NOTE: 1. VREC= Vcc - V11
SYMBOL
V17
CONDITIONS
MIN
TYP MAX UNITS
-
1.2
-
V
VREC MIN
IBIAS = 0µA (Note 1)
-
100
-
mV
VREC MAX
IBIAS = IR x 1.875 (Note 1)
-
300
-
mV
RIN17
IBIAS = IR
-
40
-
kΩ
RF
I10 = IR
-
240
-
kΩ
ISINK
(S1 closed)
-
10
-
mA
All switches remain as shown in the Test Circuit otherwise stated in the CONDITION column.
V
REG 13
+1.3 V 68n
68n
9 26 27 1
10k
B IN
5
3µ3
10n 10n
B OUT
7 30 31
I 10
DIN
10 RF
-
O+UTPUT
V CC
S1
2k2
11
DOUT
R IN 17
VBIAS
12
P GND
6
GND
17
I BIAS
All resistors in ohms, all capacitors in
farads, unless otherwise stated.
Fig. 14 Output Stage Test Circuit
COMMENTS:
1. Pin 23 and Pin 4 represent virtual ground inputs.
2. If the length of the wires between the current sources and the GP520A is
extensive, it may be necessary to connect an RC filter close to the
appropriate GP520A pin for noise immunity.
e.g.
100k
10µ
4
ICLIP
GP520A
All resistors in ohms, all capacitors in
farads, unless otherwise stated.
9
510 - 78 - 06