M5123 Datasheet, PDF (84/121 Pages) List of Unclassifed Manufacturers – Mega I/O Controller with Plug & Play

--Preliminary, Confidential, Proprietary--
Acer Laboratories Inc.
M512x : Mega I/O Controller with PnP
Table 8-4 ECP Pin Descriptions
Name
StrobeJ
Type
O
PData 7:0 I/O
AckJ
I
PeriphAck I
(Busy)
PError
I
(Ack
ReverseJ)
Select
I
AutoFdJ O
(HostAck)
FaultJ
I
(Periph
RequestJ)
InitJ
O
SelectlnJ O
Description
During write operations StrobeJ registers data or address into the
slave on the asserting edge (handshakes with Busy).
Contains address or data or RLE data.
Indicates valid data driven by the peripheral when asserted. This signal handshakes with
AutoFdJ in reverse.
This signal deasserts to indicate that the peripheral can accept data. This signal handshakes
with StrobeJ in the forward direction. In the reverse direction this signal indicates whether the
data lines contain ECP command information or data. The peripheral uses this signal to flow
control in the forward direction. It is an "interlocked" handshake with StrobeJ. PeriphAck also
provides command information in the reverse direction.
Used to acknowledge a change in the direction of the transfer (asserted= forward). The peripheral
drives this signal low to acknowledge ReverseRequestJ. It is an "interlocked" handshake with
ReverseRequestJ. The host relies upon AckReverseJ to determine when it is permitted to drive
the data bus.
Indicates printer on line.
Requests a byte of data from the peripheral when asserted, handshaking with AckJ in the reverse
direction. This signal indicates whether the data lines contain ECP address or data, the host
drives this signal to flow control in the reverse direction. It is an "interlocked" handshake with
AckJ. HostAck also provides command information in the forward phase.
Generates an error interrupt when asserted. This signal provides a mechanism or peer-to-peer
communication. This signal is valid only in the forward direction. During ECP mode, the
peripheral is permitted (but not required) to level this pin to request a reverse transfer. The
request is merely a "hint" to the host; the host has ultimate control over the transfer direction.
This signal would be typically used to generate an interrupt to the host CPU.
Sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to
place the channel in the reverse direction. The peripheral is only allowed to drive the bi-
directional data bus while in ECP Mode and HostAck is low and SelectlnJ is high.
Always deasserted in ECP mode.
Register Definitions
The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports are supported. The
additional registers attach to an upper bit decode of the standard LPT port definition to avoid conflict with standard ISA devices.
The port is equivalent to a generic parallel port interface and may be operated in that mode. The port registers vary depending on
the mode field in the ECR. The table below lists these dependencies. Operation of the devices in modes other than those specified
is undefined.
Table 8-5 ECP Register Definitions
NAME
data
ecpAFifo
dsr
dcr
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
ADDRESS (Note 1)
+000h R/W
+000h R/W
+001h R/W
+002h R/W
+400h R/W
+400h R/W
+400h R/W
+400h R
+401h R/W
+402h R/W
ECP MODES
000-001
011
All
All
010
011
110
111
111
All
FUNCTION
Data Register
ECP FIFO (Address)
Status Register
Control Register
Parallel Port Data FIFO
ECP FIFO (DATA)
Test FIFO
Configuration Register A
Configuration Register B
Extended Control Register
Note 1: These addresses are added to the parallel port base address as selected by configuration register or jumpers.
Note 2: All addresses are qualified with AEN. Refer to the AEN pin definition.
Page 84
07-02-1997 Document Number: 512xDS02.doc
Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, ROC Tel: [phone] Fax: [phone]