M5123 Datasheet, PDF (74/121 Pages) List of Unclassifed Manufacturers – Mega I/O Controller with Plug & Play

--Preliminary, Confidential, Proprietary--
Acer Laboratories Inc.
M512x : Mega I/O Controller with PnP
Register 0Bh
Index register port : 70H
Data register port : 71H
Index : 0BH
(Read/Write)
7 654
3
2
1
0
SET PIE AIE UIE SQWE DM 24/12 DSE
Bit 0. The daylight savings enable (DSE) bit is a
read/write bit which allows the program to enable two
special updates (when DSE is a "1"). On the last Sunday
of April, the time increments from 1:59:59 AM to 3:00:00
AM. On the last Sunday of October when the time first
reaches 1:59:59 AM, it changes to 1:00:00 AM. These
special updates do not occur when the DSE bit is a "0".
DSE is not changed by any internal operations or rest.
Bit 1. The 24/12 control bit establishes the format of the
hours bytes as either the 24-hour mode (a "1") or the 12-
hours mode (a "0"). This is a read/write bit, which is
affected only by software.
Bit 2. The data mode (DM) bit indicates whether time and
calendar updates are to use binary or BCD formats. The
DM bit is written by the processor program and may be
read by the program, but is not modified by any internal
functions or RESET. A "1" in DM signifies binary data,
while a "0" in DM specifies binary-coded decimal (BCD)
data.
Bit 3. When the square-wave enable (SQWE) bit is set to
a "1" by the program, a square-wave signal at the
frequency specified in the rate selection bits (RS3 to RS0)
appears on the SQW pin. When the SQWE bit is set to a
zero, the SQW pin is held low. The state of SQWE is
cleared by the RESETJ pin. SQWE is a read/write bit.
Bit 4. The UIE (update-ended interrupt enable) bit is a
read/write bit which enables the update-end flag (UF) bit in
Register C to assert IRQ. The RESETJ pin going low or
the SET bit going high clears the UIE bit.
Bit 5. The alarm interrupt enable (AIE) bit is a read/write
bit which when set to a "1" permits the alarm flag (AF) bit
in Register C to assert IRQ. An alarm interrupt occurs for
each second that the three time bytes and the three alarm
bytes (including a "don't care" alarm code of binary
11xxxxxx). When the AIE bit is a "0", the AF bit does not
initiate an IRQ signal. The RESETJ pin clears AIE to "0".
The internal functions do not affect the AIE bit.
Bit 6. The periodic interrupt enable (PIE) bit is read/write
bit which allows the periodic-interrupt flag (PF) bit in
Register C to cause the IRQ pin to be driven low. A
program writes a "1" to the PIE bit in order to receive
periodic interrupts at the rate specified by the RS3, RS2,
RS1, and RS0 bits in Register A. A zero in PIE blocks
IRQ from being initiated by a periodic interrupt, but the
periodic flag (PF) bit is still set at the periodic rate. PIE is
not modified by any internal KS82C6818A functions, but is
cleared to "0" by a RESETJ.
Bit 7. When the SET bit is a "0", the update cycle
functions normally by advancing the counts once-per-
second. When the SET bit is written to a "1", any update
cycle in progress is aborted and the program may initialize
the time and calendar bytes without an update occurring in
the midst of initializing. SET is a read/write bit which is not
modified by RESET or internal functions of the M512x.
Page 74
07-02-1997 Document Number: 512xDS02.doc
Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, ROC Tel: [phone] Fax: [phone]